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Part: CY7C09349AV-9AI
Category:
Memory
-> SRAM
-> 4 Kb
-> Multi-Port RAM
Description: Dual-port Memory 3.3V Synchronous
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C09349AV-9AI datasheet File size : 207 kB
Request For quote: Find where to buy CY7C09349AV-9AI
Datasheet text preview:
1
CY7C09349AV CY7C09359AV
3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM
Features
· True dual-ported memory cells which allow simultaneous access of the same memory location · Two Flow-Through/Pipelined devices -- 4K x 18 organization (CY7C09349AV) -- 8K x 18 organization (CY7C09359AV) · Three Modes -- Flow-Through -- Pipelined -- Burst · Pipelined output mode on both ports allows fast 83-MHz operation · 0.35-micron CMOS for optimum speed/power
v
· High-speed clock to data access 9 and 12 ns (max.) · 3.3V Low operating power -- Active = 135 mA (typical) -- Standby = 10 µA (typical) · Fully synchronous interface for easier operation · Burst counters increment addresses internally -- Shor ten cycle times -- M inimize bus noise · · · · · -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and lower byte controls for bus matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL UBL R / WR UBR
CE0L CE1L LBL OE L
1
0 /1
1
0 /1
0
0
CE0R CE1R L BR OE R
FT/PipeL
9
0 /1
1 b 0b 1a 0a
b a
0a 1 a 0b 1b
a b
0 /1
FT/PipeR
9
I/O 9LI/O 17L
9
I/O9RI/O17R I/O Control I/O Control
9
I/O 0LI/O 8L A0LA11/12L CLK L ADSL CNTEN L CNTR ST L
[1]
I/O0RI/O 8R
12 /13 12 /13
Counter/ Address Register D ecode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0RA11/12R CLKR ADSR CNTENR CNTRSTR
[1]
Notes : 1. A0A11 for 4K; A0A12 for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation · 3901 Nor th First Street · San Jose · CA 95134 · 408-943-2600 Novem ber 13, 2000
CY7C09349AV CY7C09359AV
Functional Description
The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-H IGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE 1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A por t's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Note: 2. When simultaneously writing to the same location, final value cannot be guaranteed.
2
CY7C09349AV CY7C09359AV
Pin Configuration
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL
GND
GND
A 0R
A 1R
A 2R
A 3R
A 4R
A 5R
A 6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L [3] NC NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 A 8R A 9R A10R A11R A12R [3] NC NC NC LB R UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
CY7C09359AV (8K x 18) CY7C09349AV (4K x 18)
A 7R 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/10R
A 8L
A 7L
A 6L
A 5L
A 4L
A 3L
A 2L
A 1L I/O 3L
I/O 9L
I/O 8L
I/O 7L
I/O 6L
I/O 5L
I/O 4L
I/O 2L
A 0L
I/O 1L
I/O 0L
I/O0R
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09349AV CY7C09359AV -9 fMAX2 (MHz) (Pipelined) M ax Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (µA) Shade d areas contain advance information.
Note: 3. Th is pin is NC for CY7C09349AV.
I/O9R
VCC
GND
GND
VCC
CY7C09349AV CY7C09359AV -12 50 12 115 20 10 µA
67 9 135 20 10 µA (Both Ports CMOS Level)
3
CY7C09349AV CY7C09359AV
Pin Definitions
Left Port A0LA12L ADSL R ight Port A0RA12R ADSR Description Address Inputs (A0A11 for 4K, A0A12 for 8K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte (I/O0I/O 8 for x18, I/O0I/O 7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9LI/O15/17L). O utput Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. G round Input. No Connect. Power Input. Output Current into Outputs (LOW)..... 20 mA Static Discharge Voltage .......... >2001V Latch-Up Current ..... >200 mA
CE0L,CE1L CLKL CN TENL
CE0R,CE1R CLKR CNTENR
CN TRSTL I/O0LI/O 17L LBL
CNTRSTR I/O0RI/O17R L BR
UBL O EL R/WL FT/PIPEL G ND NC VCC
UBR OE R R / WR FT/PIPE R
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......... 65°C to +150°C Ambient Temperature with Power Applied ............ 55°C to +125°C Supply Voltage to Ground Potential ...... 0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ... 0.5V to VCC+0.5V DC Input Voltage.....0.5V to VCC+0.5V
Notes : 4. Industrial parts are available in CY7C09359AV only.
Operating Range
Rang e Commercial Industrial[4] Ambient Temperature 0°C to +70°C 40°C to +85°C VCC 3.3V ± 300 mV 3.3V ± 300 mV
4
CY7C09349AV CY7C09359AV
Electrical Characteristics Over the Operating Range
CY7C09349AV CY7C09359AV -9 Parameter VOH VOL VI H VI L IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage (V CC = Min., IOH = 4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level)[5] CEL & CER VIH, f =fMAX Standby Current (One Port TTL Level) CER VIH, f =fMAX
[5]
-12 Ma x . 0. 4 Min. 2.4 0.4 2.0 0. 8 0.8 10 115 155 20 30 85 95 10 10 75 85 10 180 250 70 80 140 150 500 500 100 110 10 Typ. M ax. Unit V V V V µA mA mA mA mA mA mA µA µA mA mA
Mi n . 2.4 2.0 10 Com'l. Ind.
[4]
Typ.
135 20 95 10 85
230 75 155 500 115
Com'l. Ind.[4] CEL | Com'l. Ind.
[4]
Standby Current (Both Ports CMOS Level)[5] CEL & CER VCC 0.2V, f = 0 Standby Current (One Port CMOS Level)[5] CEL | CER VIH, f = fMAX
Com'l. Ind.[4] Com'l. Ind.
[4]
Capacitance
Parameter CIN COUT Description Input Capacitance O utput Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Ma x . 10 10 Unit pF pF
Note: 5. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
5
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