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Part: CY7C1314V18-167BZC
Category:
Memory
-> SRAM
-> Sync. SRAM
-> QDR-II
Description: Qdr-ii Synchronous SRAM
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C1314V18-167BZC datasheet File size : 207 kB
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Datasheet text preview:
PRELIMINARY
CY7C1310V18 CY7C1312V18 CY7C1314V18
18-Mb QDRTM-II SRAM Two-word Burst Architecture
Features
· Separate Independent Read and Write Data Ports -- Supports concurrent transactions · 167-MHz Clock for High Bandwidth · Two-word Burst on all accesses · Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @ 167MHz · Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only · Two output clocks (C and C) accounts for clock skew and flight time mismatches · Echo clocks (CQ and CQ) simplify data capture in high speed systems · Single multiplexed address input bus latches address inputs for both Read and Write ports · Separate Port Selects for depth expansion · Synchronous internally self-timed writes · Available in x8, x18, and x36 configurations · 1.8V core power supply with HSTL Inputs and Outputs · 13x15 mm 1.0-mm pitch FBGA package, 165 ball (11x15 matrix) · Variable drive HSTL output buffers · Extended HSTL output voltage (1.4VVDD) · JTAG Interface · On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDRTM-II architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDRTM-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310V18) or 18-bit words (CY7C1312V18) or 36-bit words (CY7C1314V18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K/K and C/C), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds." Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C/C (or K/K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1310V18 2M x 8 CY7C1312V18 1M x 18 CY7C1314V18 512K x 36
Logic Block Diagram (CY7C1310V18)
D[7:0] 8 Write Re g 1M x 8 Array
Write Add. Decode
20
Read Add. Decode
A(19:0)
Address Register
Write Re g 1M x 8 Array
Address Register
20
A(19:0)
K K
CL K Gen.
Control Logic
RPS C C
Read Data Reg. 16 Control Logic 8 Reg. 8 Reg. 8 Re g .
CQ CQ
VREF WPS BWS[1:0]
8 8 Q[7:0]
Cypress Semiconductor Corporation Document #: 38-05180 Rev. *A
·
3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 2, 2002
PRELIMINARY
Logic Block Diagram (CY7C1312V18)
D[17:0] 18 Write Reg 512K x 18 Array
Write Add. Decode
CY7C1310V18 CY7C1312V18 CY7C1314V18
19
Read Add. Decode
A(18:0)
Address Register
Write Reg 512K x 18 Array
Address Register
19
A(18:0)
K K
CL K Gen.
Control Logic
RPS C C
Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 18 Reg.
CQ CQ
VREF WPS BWS[1:0]
18 18 Q[17:0]
Logic Block Diagram (CY7C1314V18)
D[35:0] 36 Write Reg 256K x 36 Array
Write Add. Decode
18
Read Add. Decode
A(17:0)
Address Register
Write Reg 256K x 36 Array
Address Register
18
A(17:0)
K K
CL K Gen.
Control Logic
RPS C C
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 36 Reg.
CQ CQ
VREF WPS BWS[3:0]
36
36
Q[35:0]
Selection Guide[1]
200 MHz Maximum Operating Frequency Maximum Operating Current
Note: 1. Shaded cells indicate advanced information.
167 MHz 167 T BD
133 MHz 133 TBD
Unit MHz mA
200 TBD
Document #: 38-05180 Rev. *A
Page 2 of 25
PRELIMINARY
Pin Configurations
CY7C1310V18 (2M x 8) - 11 x 15 BGA
CY7C1310V18 CY7C1312V18 CY7C1314V18
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
VSS/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3
A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
VSS/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11
CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1312V18 (1M x 18) - 11 x 15 BGA
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3
D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
VSS/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
VSS/144M NC/36M
Document #: 38-05180 Rev. *A
Page 3 of 25
PRELIMINARY
Pin Configurations (continued)
CY7C1314V18 (512k x 36) - 11 x 15 BGA
CY7C1310V18 CY7C1312V18 CY7C1314V18
1 A B C D E F G H J K L M N P R
CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO
2
Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3
D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A
10
Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
VSS/288M NC/72M
NC/36M VSS/144M
Document #: 38-05180 Rev. *A
Page 4 of 25
PRELIMINARY
Pin Definitions
Pin Name D[x:0] I/O InputSynchronous Pin Description
CY7C1310V18 CY7C1312V18 CY7C1314V18
Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1310V18 - D[7:0] CY7C1312V18 - D[17:0] CY7C1314V18 - D[35:0] Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1310V18 - BWS0 controls D[3:0] and BWS1 controls D[7:4]. CY7C1312V18 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1314V18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310V18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1312V18 and 256K x 36 (2 arrays each of 256K x 36) for CY7C1314V18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1310V18, 19 address inputs for CY7C1312V18 and 18 address inputs for CY7C1314V18. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. CY7C1310V18 - Q[7:0] CY7C1312V18 - Q[17:0] CY7C1314V18 - Q[35:0] Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table.
WPS
InputSynchronous InputSynchronous
BWS0, BWS1, BWS2, BWS3
A
InputSynchronous
Q[x:0]
OutputsSynchronous
RPS
InputSynchronous
C
InputClock Input-Clock
C
K
Input-Clock
K CQ
Input-Clock Echo Clock
CQ
Echo Clock
Document #: 38-05180 Rev. *A
Page 5 of 25
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
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