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Part: CY7C1317V18-167BZC
Category:
Description: 18-Mb Ddr-ii SRAM Four-word Burst Architecture
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C1317V18-167BZC datasheet File size : 207 kB
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PRELIMINARY
CY7C1317V18 CY7C1319V18 CY7C1321V18
18-Mb DDR-II SRAM Four-word Burst Architecture
Features
· 18-Mb density (2M x 8, 1M x 18, 512K x 36) -- Supports concurrent transactions · 250-MHz clock for high bandwidth · Four-word burst for reducing address bus frequency · Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz · Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only · Two output clocks (C and C) accounts for clock skew and flight time mismatches · Echo clocks (CQ and CQ) simplify data capture in high speed systems · Synchronous internally self-timed writes · 1.8V core power supply with HSTL inputs and outputs · Variable drive HSTL output buffers · Expanded HSTL output voltage (1.4VVDD) · 13 x 15 mm 1.0-mm pitch fBGA package, 165-ball (11 x 15 matrix) · JTAG interface · On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1317V18/CY7C1319V18/CY7C1321V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with four 8-bit words in the case of CY7C1317V18 that burst sequentially into or out of the device. The burst counter always starts with "00" internally in the case of CY7C1317V18. On CY7C1319V18 and CY7C1321V18, the burst counter takes in the last two significant bits of the external address and bursts four 18-bit words in the case of CY7C1319V18, and four 36-bit words in the case of CY7C1321V18, sequentially into or out of the device. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1317V18 2M x 8 CY7C1319V18 1M x 18 CY7C1321V18 512K x 36
Logic Block Diagram (CY7C1317V18)
Burst Logic
A(18:0) 19 LD K K
Write Add. Decode
Read Add. Decode
Address Register
Write Write Write Write Reg Reg Reg Reg
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
8 Output Logic Control R/W C C CQ CQ 8 8
CLK Gen.
Read Data Reg. 32 Control Logic 16 Re g . 16 Re g . Re g .
VREF R/W BWS[1:0]
DQ[7:0]
Cypress Semiconductor Corporation Document #: 38-05178 Rev. *A
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CA 95134 · 408-943-2600 Revised July 31, 2002
PRELIMINARY
Logic Block Diagram (CY7C1319V18)
A(1:0) 2 20 A(19:0)
18
CY7C1317V18 CY7C1319V18 CY7C1321V18
Burst Logic
Write Add. Decode
Read Add. Decode
Address A(19:2) Register LD
Write Write Write Write Reg Reg Reg Reg
256K x 18 Array
256K x 18 Array
256K x 18 Array
256K x 18 Array
18
K K
CL K Gen.
Output Logic Control
R/W C C
Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 18 Reg.
CQ CQ 18 DQ[17:0]
VREF R/W BWS[1:0]
Logic Block Diagram (CY7C1321V18)
A(1:0) 2 19 A(18:0)
17
Burst Logic
Write Add. Decode
Read Add. Decode
Address A(18:2) Register LD
Write Write Write Write Reg Reg Reg Reg
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
36
K K
CL K Gen.
Output Logic Control
R/W C C CQ CQ 36 DQ[35:0]
Read Data Reg. 144 Control Logic 72 Reg. 72 Reg. 36 Reg.
VREF R/W BWS[3:0]
Selection Guide[1]
300 MHz Maximum Operating Frequency Maximum Operating Current
Note: 1. Shaded cells indicate advanced information.
250 MHz 250 T BD
200 MHz 200 TBD
167 MHz 167 T BD
Unit MHz mA
300 TBD
Document #: 38-05178 Rev. *A
Page 2 of 23
PRELIMINARY
Pin Configurations
CY7C1317V18 (2M x 8) - 11 x 15 FBGA
CY7C1317V18 CY7C1319V18 CY7C1321V18
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
VSS/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK
3
A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
VSS/36M NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS
11
CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI
CY7C1319V18 (1M x 18) - 11 x 15 FBGA
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
VSS/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK
3
A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
NC BWS0 A1 VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
VSS/36M NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS
11
CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
Document #: 38-05178 Rev. *A
Page 3 of 23
PRELIMINARY
Pin Configurations (continued)
CY7C1321V18 (512K x 36) - 11 x 15 FBGA
CY7C1317V18 CY7C1319V18 CY7C1321V18
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK
3
DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A
4
R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7
BWS1 BWS0 A1 VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
VSS/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS
11
CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
VSS/144M NC/36M
Pin Definitions
Pin Name DQ[x:0] I/O Pin Description Input/Output- Data input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Synchronous write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. CY7C1317V18 - DQ[7:0] CY7C1319V18 - DQ[17:0] CY7C1321V18 - DQ[35:0] InputSynchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. Synchronous This definition includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods of bus activity). InputByte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1311V18 - BWS0 controls D[3:0] and BWS1 controls D[7:4]. CY7C1313V18 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1315V18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. InputAddress inputs. These address inputs are multiplexed for both Read and Write operations. Synchronous Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1317V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1319V18 and 256K x 36 (four arrays each of 128K x 36) for CY7C1321V18. CY7C1317V18 Since the least two significant bits of the address internally are "00," only 19 address inputs are needed to access the entire memory array. CY7C1319V18 A0 and A1 are the inputs to the burst counter. These are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. CY7C1321V18 A0 and A1 are the inputs to the burst counter. These are incremented in a linear fashion internally. 19 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected.
LD
BWS0, BWS1, BWS2, BWS3
A, A0, A1
Document #: 38-05178 Rev. *A
Page 4 of 23
PRELIMINARY
Pin Definitions (continued)
Pin Name R/W I/O Pin Description
CY7C1317V18 CY7C1319V18 CY7C1321V18
InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (Read Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K. InputClock InputClock InputClock InputClock Echo Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, "DLL Operation in the QDRTM-II." TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. No connects. Can be tied to any voltage level. Address expansion for 36M. This is not connected to the die. Address expansion for 72M. This is not connected to the die and so can be tied to any voltage level. Address expansion for 72M. This must be tied LOW on the 18M SRAM. Address expansion for 144M. This must be tied LOW on the 18M SRAM. Address expansion for 288M. This must be tied LOW on the 18M SRAM. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Ground for the device. Should be connected to ground of the system.
C
C
K
K CQ
CQ
Echo Clock
ZQ
Input
DOFF
Input
TDO TCK TDI TMS NC NC/36M NC/72M VSS/72M VSS/144M VSS/288M VREF VDD VSS VDDQ
Output Input Input Input Input Input Input Input Input Input InputReference Ground
Power Supply Power supply inputs to the core of the device. Should be connected to 1.8V power supply. Power Supply Power supply inputs for the outputs of the device. Should be connected to 1.5V power supply.
Document #: 38-05178 Rev. *A
Page 5 of 23
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
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