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Part: CY7C132-30M
Category:
Memory
-> SRAM
-> SRAM
Description: 2kx8 Dual-port Static RAM
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C132-30M datasheet File size : 207 kB
Request For quote: Find where to buy CY7C132-30M
Datasheet text preview:
1CY 7 C13 2/ CY7 C1 36
fax id: 5201
CY 7C132/ CY7C136 CY 7C142/ CY7C146
2Kx8 Dual-Port Static RAM
Features
· True Dual-Ported memory cells which allow simultaneous reads of the same memory location · 2K x 8 organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low operating power: ICC = 90 mA (max.) · Fully asynchronous operation · Automatic power-down · Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 · BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146 · INT flag for port-to-port communication (52-pin PLCC/PQFP versions) · Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146) · Pin-compatible and functionally equivalent to IDT7132/IDT7142
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
R/WL CEL OEL
Pin Configuration
R/WR CER OER CEL R/WL BUSYL A1 0L OEL A0 L A1 L A2 L A3 L A4 L A5 L A6 L A7 L A8 L A9 L I/O0 L I/O1 L I/O2 L I/O3 L I/O4 L I/O5 L I/O6 L I/O7 L GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 1 2 7C132 1 3 7C142 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CER R/WR BUSYR A1 0R OER A0 R A1 R A2 R A3 R A4 R A5 R A6 R A7 R A8 R A9 R I/O7 R I/O6 R I/O5 R I/O4 R I/O3 R I/O2 R I/O1 R I/O0 R C132-2
I/O7 L I/O0 L BUSYL[1] A 10L A 0L
I/O CONT ROL
I/O CO NTROL
I/O7 R I/O0 R BUSYR[1]
ADDRESS DECODER
MEMORY ARRAY
ADDRESS DECODER
A 1 0R A 0R
CEL OEL R/WL INTL[2]
ARBIT RA IO N T LOG IC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY)
CER OER R/WR INTR[2] C132-1
Notes: 1. CY7 C132/CY 7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose · CA 95134 · 408-943-2600 December 1989 Revised March 27, 1997
CY7C132/CY7C136 CY7C142/CY7C146
Pin Configurations (continued)
PLCC Top View PQFP Top View
A1 L A2 L A3 L A4 L A5 L A6 L A7 L A8 L A9 L I/O0 L I/O1 L I/O2L I/O3L
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33
OER A0 R A1 R A2 R A3 R A4 R A5 R A6 R A7 R A8 R A9 R NC I/O7 R
52 51 50 49 48 47 46 45 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2 L I/O3 L 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 7C136 33 7C146 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 OER A0 R A1 R A2 R A3 R A4 R A5 R A6 R A7 R A8 R A9 R NC I/O7 R C132-4
C132-3
Selection Guide
7C132-25[3] 7C136-25 7C136-15[3,4] 7C142-25 7C146-25 7C146-15 15 25 190 170 7C132-30 7C136-30 7C142-30 7C146-30 30 170 7C132-35 7C136-35 7C142-35 7C146-35 35 120 170 75 65 65 45 65 7C132-45 7C136-45 7C142-45 7C146-45 45 90 120 35 45 7C132-55 7C136-55 7C142-55 7C146-55 55 90 120 35 45
Maximum Access Time (ns) Maximum Operating Com'l/Ind Current (mA) Maximum Operating Military Current (mA) Maximum Standby Com'l/Ind Current (mA) Military
Notes: 3. 15 and 25-ns version available in PQFP and PLCC packages only. 4. Sha ded area contains preliminary information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .... -65°C to +150°C Ambient Temperature with Power Applied........ -55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24).......-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ..... - 0.5V to +7.0V DC Input Voltage ....... -3.5V to +7.0V Output Current into Outputs (LOW) ..... 20 mA
]
Static Discharge Voltage ......... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .... >200 mA
Operating Range
R ange Com mercial Industrial Military[5] Ambient Tem perature 0°C to +70°C -40°C to +85°C -55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10%
Note: 5. TA is the "instant on" case temperature.
2
CY7C132/CY7C136 CY7C142/CY7C146
Electrical Characteristics Over the Operating Range[6]
7C132-30[3] 7C136-25,30 7C142-30 7C136-15[3,4] 7C146-25,30 7C146-15 Parameter Description VOH VOL VIH VIL IIX IOZ IOS ICC Test Conditions M in. 2.4 0.4 0.5 2.2 0.8 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND CE = VIL, Outputs Open, f = fMAX[9] Com'l Mil 75 65 -5 -5 +5 +5 -350 190 -5 -5 2.2 0.8 +5 +5 -350 170 -5 -5 M ax. Min. 2.4 0.4 0.5 2. 2 0. 8 +5 +5 -350 120 170 45 65 135 115 90 115 15 15 15 15 125 105 85 105 -5 -5 Max. O utput HIGH Voltage VCC = Min., IOH = -4.0 mA O utput LOW Voltage IOL = 4.0 mA IOL = 16.0 mA[7] Input HIGH Voltage Input LOW Voltage Input Load Current O utput Leakage Cur rent O utput Short Circuit Current[8] VCC Operating Supply Current Standby Current Both Ports, TTL Inputs Standby Current O ne Port, TTL Inputs Standby Current Both Ports, CMOS Inputs Standby Current O ne Port, CMOS Inputs 7C132-35 7C136-35 7C142-35 7C146-35 Min. Max. 2. 4 0. 4 0. 5 2. 2 0.8 +5 +5 -350 90 120 35 45 75 90 15 15 70 85 mA mA mA mA 7C132-45,55 7C136-45,55 7C142-45,55 7C146-45,55 Min. 2. 4 0.4 0.5 V V µA µA mA mA M ax. Unit V V
ISB1
CEL and CER > VIH, Com'l f = fMAX[9] Mil CEL or CER > VIH, Com'l Active Port Outputs Mil Open, [9] f = fMAX Both Ports CEL and CER > VCC 0.2V, VIN > VCC 0.2V or VIN VCC 0.2V, VIN > VCC 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[9] Com'l Mil Com'l Mil
ISB2
ISB3
ISB4
]
Capacitance[10]
Parameter CIN COUT Descri ption Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF
Notes: 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Durati on of the short circuit should not exceed 30 seconds. 9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 10. Thi s parameter is guaranteed but not tested.
3
CY7C132/CY7C136 CY7C142/CY7C146
AC Test Loads and Waveforms
5V OUTPU T 30 pF INCL UDING JIGAND SCOPE R2 347 R1 893 5V OUTP UT 5 pF INCL UDING JIGAND SCOPE R2 347
C132-5
R1893
5V 281
BUS Y OR INT
30pF
(a)
(b)
C132-6
BUSY Output Load (CY7C132/CY7C136 ONLY)
ALL INPUT PULSES
Eq ui vale nt to :
THVÉNIN EQUIVAL ENT 3.0V 250 1.4V 10%
90%
OUTP UT
GND
90% 10% < 5 ns
< 5 ns
]
Switching Characteristics Over the Operating Range[6, 11]
7C136-15[3,4] 7C146-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid
[12]
7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. 25 Max.
7C132-30 7C136-30 7C142-30 7C146-30 Min. 30 M ax. Unit ns 30 0 30 20 3 15 5 15 0 25 30 25 25 2 0 25 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 0 ns ns
Description
Min. 15
Max.
15 0 15 10 3 10 3 10 0
[10]
25 0 25 15 3 15 5 15 0 25 25 20 20 2 0 15 15 0
Data Hold from Address Change CE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low Z CE LOW to
[15] [12]
OE LOW to Data Valid[12]
[10, 13]
Z[10, 13, 14]
[10, 13]
CE HIGH to High Z[10, 13, 14] Power-Up[10] CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z [10] R/W HIGH to Low Z
[10]
15 15 12 12 2 0 12 10 0 10 0 0
15
4
CY7C132/CY7C136 CY7C142/CY7C146
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C136-15[3,4] 7C146-15 Parameter BUSY/INTERRUPT TIMING tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[16] 5 0 13 15 Note 18 Note 18 15 15 15 15 15 15 Port Set Up for Priority R/W LOW after BUSY LOW[17] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Mismatch[16] 15 15 15 15 5 0 20 25 Note 18 Note 18 25 25 25 25 25 25 20 20 20 20 5 0 30 30 Not e 18 Not e 18 25 25 25 25 25 25 20 20 20 20 ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. M ax. Unit
INTERRUPT TIMING[19] tWINS tEINS tINS tOINR tEINR tINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[16]
[16]
ns ns ns ns ns ns
CE to INTERRUPT Reset Time
Address to INTERRUPT Reset Time[16]
Switching Characteristics Over the Operating Range[6, 11]
7C132-35 7C136-35 7C142-35 7C146-35 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid
[12]
7C132-45 7C136-45 7C142-45 7C146-45 Min. 45 Max.
7C132-55 7C136-55 7C142-55 7C146-55 Min. 55 M ax. Unit
Description
Min. 35
Max.
ns 55 ns ns 55 25 ns ns ns 25 ns ns 25 ns ns 35 ns
35 0 35 20 3 20 5 20 0
[10]
45 0 45 25 3 20 5 20 0 0 35 5 3 0
Data Hold from Address Change CE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[12]
OE LOW to Data Valid[12]
[10, 13] [10, 13, 14]
OE HIGH to High Z
[10, 13]
CE HIGH to High Z[10, 13, 14] CE LOW to Power-Up
[10]
CE HIGH to Power-Down
35
5
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