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Details, datasheet, quote on part number:CY7C1354B-200BGC
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Datasheet text preview:
PRELIMINARY
CY7C1354B CY7C1356B
256K x 36/512K x 18 Pipelined SRAM with NoBLTM Architecture
Features
· Pin-compatible and functionally equivalent to ZBTTM · Supports 250-MHz bus operations with zero wait states -- Available speed grades are 250, 200 and 166 MHz · Internally self-timed output buffer control to eliminate the need to use asynchronous OE · Fully registered (inputs and outputs) for pipelined operation · Byte Write capability · Separate VDDQ for 3.3V or 2.5V I/O · Single 3.3V power supply · Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 3.0ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) · Clock Enable (CEN) pin to suspend operation · Synchronous self-timed writes · Available in 100 TQFP, 119 BGA, and 165 fBGA packages · IEEE 1149.1 JTAG-compatible Boundary Scan · Burst capability--linear or interleaved burst order ·"ZZ" Sleep Mode option and Stop Clock option LatencyTM (NoBL) logic, respectively. They are designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1354B and CY7C1356B are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1354B and CY7C1356B are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device). Write operations are controlled by the Byte Write Selects (BWSaBWSd for CY7C1354B and BWSaBWSb for CY7C1356B) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Functional Description
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus
Logic Block Diagram
CLK CE ADV/LD Ax CEN CE1 CE2 CE3 WE CY7C1354B CY7C1356B BWSx AX DQ X DQPX BWSX
X = 17:0 X = a, b, c, d X = a, b, c, d X = a, b, c, d X = 18:0 X = a, b X = a, b X = a, b
D Data-In REG. Q OUTPUT REGISTERS and LOGIC
CONTROL and WRITE LO G I C
256K X36/ 512K X18 MEMORY ARRAY
DQ x DQP x
M ode
OE
Selection Guide
CY7C1354B-250 CY7C1356B-250 Maximum Access Time Maximum Operating Current Com'l Maximum CMOS Standby Current Com'l 2.6 250 30 CY7C1354B-200 CY7C1356B-200 3.0 220 30 CY7C1354B-166 CY7C1356B-166 3.5 180 30 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05114 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 16, 2002
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A
CY7C1354B CY7C1356B
A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A
NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb NC DQa VSS VSS VDDQ V
DDQ
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VS S VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQa DQa DQPa NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1354B (256K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CY7C1356B (512K x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0
E(288) E(144)
VSS VDD
E(36)
A A A A A A A
MODE A A A A A1 A0
E(72)
E(288) E(144)
E(72)
VSS VDD
Document #: 38-05114 Rev. **
E(36)
A A A A A A
Page 2 of 25
A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout CY7C1354B (256K x 36)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQ c VDDQ DQ c DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
CY7C1354B CY7C1356B
2
A CE2 A DQPc DQc DQ c DQc DQ c VDD DQd DQd DQd DQd DQPd A E(72) TMS
3
A A A VSS VSS VSS BWSc VSS NC VSS BWSd VSS VSS VSS MODE A TDI
4
E(18) ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BW Sb VSS NC VSS BWSa VSS VSS VSS NC A TDO
6
A CE3 A DQPb DQ b DQb DQ b DQb VDD DQ a DQa DQ a DQa DQPa A E(36) NC
7
VDDQ NC NC DQ b DQb VDDQ DQb DQ b VDDQ DQa DQ a VDDQ DQ a DQa NC ZZ VDDQ
CY7C1356B (512K x 18)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC E(72) VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS
3
A A A VSS VSS VSS BWSb VSS NC VSS VSS VSS VSS VSS MODE A TDI
4
E(18) ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD E(36) TCK
5
A A A VSS VSS VSS VSS VSS NC VSS BWSa VSS VSS VSS NC A TDO
6
A CE3 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Document #: 38-05114 Rev. **
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PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1354B CY7C1356B
1 A B C D E F G H J K L M N P R
E(288) NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE
2
A A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
CY7C1354B (256K x 36)13 x 15 fBGA 4 5 6 7
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
8
ADV/LD
9
A E(18)
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC E(144) DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
CE3 CLK
CEN WE
OE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
CY7C1356B (512K x 18)13 x 15 fBGA
1 A B C D E F G H J K L M N P R
E(288) NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
2
A A NC DQb DQb DQb DQb VDD NC NC NC NC NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD
9
A E(18)
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A E(144) DQPb DQb DQb DQb DQb ZZ NC NC NC NC NC NC A
OE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05114 Rev. **
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PRELIMINARY
Pin Definitions
Pin Name A0 A1 A BWSa BWSb BWSc BWSd WE ADV/LD I/O Type InputSynchronous InputSynchronous Pin Description
CY7C1354B CY7C1356B
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DQPa, BWSb controls DQb and DQPb, BWSc controls DQc and DQPc, BWSd controls DQd and DQPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQaDQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWSa, DQPb is controlled by BWSb, DQPc is controlled by BWSc, and DQPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.
InputSynchronous InputSynchronous
CLK CE1 CE2 CE3 OE
InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous I/OSynchronous
DQa DQb DQc DQd
DQPa DQPb DQPc DQPd MODE
I/OSynchronous
Input Strap Pin
TDO TDI TMS TCK VDD VDDQ
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous JTAG-Clock Power Supply Clock input to the JTAG circuitry. Power supply for the 3.3V control logic.
I/O Power Supply Either 3.3V or 2.5V power supply for the I/O circuitry.
Document #: 38-05114 Rev. **
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