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Details, datasheet, quote on part number:CY7C1354BV25
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Datasheet text preview:
CY7C1356BV25 PRELIMINARY CY7C1354BV25
256K x 36/512K x 18 Pipelined SRAM with NoBLTM Architecture
Features
· Pin compatible and functionally equivalent to ZBT · Supports 250-MHz bus operations with zero wait states -- Available speed grades are 250, 200 and 166 MHz · Internally self-timed output buffer control to eliminate the need to use asynchronous OE · Fully Registered (inputs and outputs) for pipelined operation · Byte Write capability · Common I/O architecture · Single 2.5V power supply · Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 3.0 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) · Clock Enable (CEN) pin to suspend operation · Synchronous self-timed writes · Available in 100 TQFP, 119 BGA, and 165 fBGA Packages ·IEEE 1149.1 JTAG-compatible boundary scan · Burst capability--linear or interleaved burst order ·"ZZ" Sleep Mode option and Stop Clock option NoBLTM logic, respectively. They are designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1354BV25 and CY7C1356BV25 are equipped with the advanced No Bus LatencyTM (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1354BV25 and CY7C1356BV25 are pin compatible and functionally equivalent to ZBTTM devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device). Write operations are controlled by the Byte Write Selects (BWSaBWSd for CY7C1354BV25 and BWSaBWSb for CY7C1356BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous-Pipelined Burst SRAMs with
Logic Block Diagram
CLK CE ADV/LD Ax CEN CE1 CE2 CE3 WE BWSx M ode CONTROL and WRITE LO G I C 256K X36/ 512K X18 MEMORY ARRAY OUTPUT REGISTERS and LOGIC D Data-In REG. Q
DQ x DQP x
CY7C1 354 AX DQ X DQPX BWSX
X = 17:0 X = a, b, c, d X = a, b, c, d X = a, b, c, d
CY7C1 356
X = 18:0 X = a, b X = a, b X = a, b
OE
Cypress Semiconductor Corporation Document #: 38-05292 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 15, 2002
CY7C1356BV25 PRELIMINARY
Selection Guide
7C1354BV25-250 7C1356BV25-250 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Com'l Com'l 2.6 250 30 7C1354BV25-200 7C1356BV25-200 3.0 220 30 7C1354BV25-166 7C1356BV25-166 3.5 180 30 Unit ns mA mA
CY7C1354BV25
Pin Configurations
A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A
A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS C LK WE C EN OE AD V/L D E( 18 ) A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP Packages
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VS S VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQ d VSS VDDQ DQ d DQ d Q Pd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1354BV25 (256K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb DQ b VD D Q VS S
NC NC NC VDDQ VSS NC NC DQb DQb VS S VD D Q
1 00 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQb DQb DQb DQb VS S VD D Q DQb DQb DQb DQb NC VS S VDD NC NC VD D VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VS S DQa DQb DQa DQb DQa DQPb NC DQa VS S VSS VD D Q VD D Q NC DQ a NC DQa DQPa NC
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VD D ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1356BV25 (512K x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0
MODE A A A A A1 A0
E(288) E(144)
VSS VDD
E(36)
A A A A A A A
E(288) E(144)
E(72)
VSS VD D
Document #: 38-05292 Rev. *A
E(72)
E(36)
A A A A A A
Page 2 of 25
A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CY7C1356BV25 PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout CY7C1354BV25 (256K x 36)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
V DDQ NC NC DQ c DQ c V DDQ DQ c DQ c V DDQ DQd DQd V DDQ DQd DQd NC NC V DDQ
CY7C1354BV25
2
A C E2 A DQPc DQ c DQ c DQ c DQ c V DD DQd DQd DQ d DQd D Q Pd A E(72) TMS
3
A A A VS S VS S VS S BW S c VS S NC VS S BW Sd VS S VS S VS S MODE A T DI
4
E(18) ADV/L D V DD NC C E1 OE A WE V DD CLK NC CEN A1 A0 V DD A T CK
5
A A A VSS VSS VSS BW Sb VSS NC VSS B W Sa VSS VSS VSS NC A TD O
6
A C E3 A DQPb DQ b DQ b DQ b DQ b V DD DQ a DQ a DQ a DQ a DQPa A E(36) NC
7
V DDQ NC NC DQ b DQ b V DDQ DQ b DQ b V DDQ DQ a DQ a V DDQ DQ a DQ a NC ZZ V DDQ
CY7C1356BV25 (512K x 18)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
V DDQ NC NC DQb NC V DDQ NC DQb V DDQ NC DQb V DDQ DQb NC NC E(72) V DDQ
2
A C E2 A NC DQb NC DQb NC V DD DQb NC DQb NC D Q Pb A A T MS
3
A A A VSS VSS VSS B W Sb VSS NC VSS VSS VSS VSS VSS MO D E A TD I
4
E(18) ADV/L D V DD NC C E1 OE A WE V DD CLK NC CEN A1 A0 V DD E(36) T CK
5
A A A VSS VSS VSS VSS VSS NC VSS BW Sa VSS VSS VSS NC A TD O
6
A C E3 A D Q Pa NC DQ a NC DQ a V DD NC DQ a NC DQ a NC A A NC
7
V DDQ NC NC NC DQa V DDQ DQa NC V DDQ DQa NC V DDQ NC DQa NC ZZ V DDQ
Document #: 38-05292 Rev. *A
Page 3 of 25
CY7C1356BV25 PRELIMINARY
Pin Configurations (continued)
165-ball fBGA Pinout
CY7C1354BV25
1 A B C D E F G H J K L M N P R
E(288) NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE
2
A A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC E(72) E(36)
CY7C1354BV25 (256K x 36)13 x 15 fBGA 3 4 5 6 7 8
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
9
A E(18)
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC E(144) DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
CE3 CLK
CEN WE
ADV/LD
OE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
CY7C1356BV25 (512K x 18)13 x 15 fBGA
1 A B C D E F G H J K L M N P R
E(288) NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
2
A A NC DQb DQb DQb DQb VDD NC NC NC NC NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD
9
A NC
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A E(144) DQPb DQb DQb DQb DQb ZZ NC NC NC NC NC NC A
OE
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05292 Rev. *A
Page 4 of 25
CY7C1356BV25 PRELIMINARY
Pin Definitions
Pin Name A0 A1 A BWSa BWSb BWSc BWSd WE ADV/LD I/O Type InputSynchronous InputSynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DQPa, BWSb controls DQb and DQPb, BWSc controls DQc and DQPc, BWSd controls DQd and DQPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQaDQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWSa, DQPb is controlled by BWSb, DQPc is controlled by BWSc, and DQPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Clock input to the JTAG circuitry.
CY7C1354BV25
InputSynchronous InputSynchronous
CLK CE1 CE2 CE3 OE
InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous
DQa DQb DQc DQd
I/OSynchronous
DQPa DQPb DQPc DQPd MODE
I/OSynchronous
Input Strap Pin
TDO TDI TMS TCK
JTAG serial output Synchronous JTAG serial input Synchronous Test Mode Select Synchronous JTAG-Clock
Document #: 38-05292 Rev. *A
Page 5 of 25
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