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Details, datasheet, quote on part number:CY7C1354V25-100AC
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Datasheet text preview:
356V 25
PRELIMINARY
CY7C1354V25 CY7C135 6V25
256Kx36/512Kx18 Pipelined SRAM with NoBLTM Architecture
Features
· Pin compatible and functionally equivalent to ZBTTM · Supports 200-MHz bus operations with zero wait states -- Data is transferred on every clock · Internally self-timed output buffer control to eliminate the need to use asynchronous OE · Fully Registered (inputs and outputs) for pipelined operation · Byte Write capability · Common I/O architecture · Single 2.5V power supply · Fast clock-to-output times -- 3.2 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) -- 4.2 ns (for 133-MHz device) · · · · -- 5.0 ns (for 100-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Available in 100 TQFP & 119 BGA Packages Burst Capability--linear or interleaved burst order spectively. They are designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1354V25/CY7C1356V25 is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1354V25/CY7C1356V25 is pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.2 ns (200-MHz device). Write operations are controlled by the Byte Write Selects (BWSaBWSd for CY7C1354V25 and BWSaBWSb for CY7C1356V25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Functional Description
The CY7C1354V25 and CY7C1356V25 are 2.5V, 256K by 36 and 512K by 18 Synchronous-Pipelined Burst SRAMs, re-
Logic Block Diagram
CLK CE ADV/LD Ax CEN CE1 CE2 CE3 WE BWSx M ode CONTROL and WRITE LO G I C 256K X36/ 512K X18 MEMORY ARRAY OUTOUT REGISTERS and LOGIC D Data-In REG. Q
DQ x DP x
CY7C1 354 AX DQ X DPX BWSX
X = 17:0 X = a, b, c, d X = a, b, c, d X = a, b, c, d
CY7C1 356
X = 18:0 X = a, b X = a, b X = a, b
OE
.
Selection Guide
7C1354V25-200 7C1354V25-166 7C1354V25-133 7C1354V25-100 7C1356V25-200 7C1356V25-166 7C1356V25-133 7C1356V25-100 Maximum Access Time (ns) Maximum Operating Current (mA) Com'l Maximum CMOS Standby Current (mA) Com'l 3.2 475 10 3.5 450 10 4.0 370 10 5.0 300 10
Shaded areas contain advance information. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation Document #: 38-05263 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised March 6, 2002
PRELIMINARY
Pin Configurations
CY7C1354V25 CY7C1356V25
100-Pin TQFP Packages
A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD NC A
A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD NC A
DPb DQb DQb VDDQ VSS
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DPc DQc DQc VDDQ
VSS DQc DQc DQc DQc VSS VDDQ DQc DQc SN VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1354V25 (256K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb SN VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DPb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VDD VDD NC DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DPa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DPa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD NC DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1356V25 (512K x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 DNU DNU VSS VDD
DNU DNU A A A A A A A
MODE A A A A A1 A0 DNU DNU VSS VDD
Document #: 38-05263 Rev. **
DNU DNU A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 2 of 27
PRELIMINARY
Pin Configurations (continued)
119-Ball Bump BGA CY7C1354 (256K x 36) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQ d DQd VDDQ DQd DQ d NC 64M VDDQ
CY7C1354V25 CY7C1356V25
2
A CE2 A DPc DQc DQc DQc DQc VDD DQd DQ d DQd DQ d DPd A NC TMS
3
A A A VSS VSS VSS BWSc VSS VDD(1) VSS BWSd VSS VSS VSS MODE A TDI
4
16M ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BW S b VSS VDD(1) VSS BWSa VSS VSS VSS SN A TDO
6
A CE3 A DPb DQ b DQb DQ b DQb VDD DQ a DQa DQ a DQa D Pa A 32M DNU
7
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC NC VDDQ
CY7C1356(512K x 18) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC 64M VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DPb A A TMS
3
A A A VSS VSS VSS BWSb VSS VDD(1) VSS VSS VSS VSS VSS MODE A TDI
4
16M ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD 32M TCK
5
A A A VSS VSS VSS VSS VSS VDD(1) VSS BWSa VSS VSS VSS SN A TDO
6
A CE3 A DPa NC DQa NC DQa VDD NC DQa NC DQa NC A A DNU
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC NC VDDQ
Document #: 38-05263 Rev. **
Page 3 of 27
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location 37, 36, 3235, 4450, 8083, 99, 100 93, 94 x36 Pin Location 37, 36, 3235, 4450, 81-83, 99, 100 93, 94, 95, 96 Name A0 A1 A BWSa BWSb BWSc BWSd WE I/O Type InputSynchronous InputSynchronous Description
CY7C1354V25 CY7C1356V25
Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
88
88
InputSynchronous InputSynchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE1
InputSynchronous InputSynchronous InputSynchronous
97
97
CE2
92
92
CE3
86
86
OE
InputOutput Enable, active LOW. Combined with the synchroAsynchronous nous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQaDQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63, 68, 69, 7274 (b)8, 9, 12, 13, 18, 19, 2224
(a)52, 53, 5659, 62, 63, (b)68, 69, 7275, 78, 79 (c)2, 3, 69, 12, 13, (d)18, 19, 2225, 28, 29
DQa DQb DQc DQd
I/OSynchronous
Document #: 38-05263 Rev. **
Page 4 of 27
PRELIMINARY
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location 74, 24 x36 Pin Location 51, 80, 1, 30 Name DPa DPb DPc DPd MODE I/O Type I/OSynchronous Description
CY7C1354V25 CY7C1356V25
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.
31
31
Input Strap Pin
14 15, 16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
14 15, 16, 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
SN VDD VDDQ VSS
InputThis is a reserved pin. Tie it to VDD for normal operation. Asynchronous Power Supply I/O Power Supply Ground Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. Should be connected to ground of the system. No connects. Reserved for address expansion to 512K depths. Do Not Use pins. These pins should be left floating.
NC 38, 39, 42, 43 38, 39, 42, 43 DNU
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Pin Definitions (119 BGA)
x18 Pin Location P4, N4, A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, G4, R2, R6, T2, T3, T5, T6 L5, G3 x36 Pin Location P4, N4, A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, R2, R6, G4, T3, T4, T5 L5, G5, G3, L3 Name A0 A1 A BWSa BWSb BWSc BWSd WE I/O Type InputSynchronous Description Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Page 5 of 27
InputSynchronous
H4
H4
InputSynchronous InputSynchronous
B4
B4
ADV/LD
K4
K4
CLK
Input-Clock
E4
E4
CE1
InputSynchronous InputSynchronous
B2
B2
CE2
Document #: 38-05263 Rev. **
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