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Details, datasheet, quote on part number:CY7C1355A-117AI
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Datasheet text preview:
CY7C1357A CY7C1355A
256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBLTM Architecture
Features
· Zero Bus Latency, no dead cycles between write and read cycles · Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns · Fast clock speed: 133, 117, and 100 MHz · Fast OE access time: 6.5, 7.0, and 7.5ns · Internally synchronized registered outputs eliminate the need to control OE · · · · · · · · · · · 3.3V 5% and +5% power supply 3.3V or 2.5V I/O supply Single WEN (READ/WRITE) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear four-word burst capability Individual byte write (BWaBWd) control (may be tied LOW) CEN pin to enable clock and suspend operations Three chip enables for simple depth expansion Automatic Power-down feature available using ZZ mode or CE deselect. JTAG boundary scan (except CY7C1357A) Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array) for CY7C1355A, and 100-pin TQFP packages for both devices All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and read-write control (WEN). BWc and BWd apply to CY7C1355A only. Address and control signals are applied to the SRAM during one clock cycle, and one cycle later, its associated data occurs, either read or write. A Clock Enable (CEN) pin allows operation of the CY7C1355A/CY7C1357A to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is HIGH and the internal device registers will hold their previous values. There are three Chip Enable pins (CE, CE2, CE3) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated. The CY7C1355A and CY7C1357A have an on-chip 2-bit burst counter. In the burst mode, the CY7C1355A and CY7C1357A provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH) Output Enable (OE), Sleep Enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. 7C1355A-117 7C1357A-117 7 385 30 7C1355A-100 7C1357A-100 7.5 350 30
Functional Description
The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors.
Selection Guide
7C1355A-133 7C1357A-133 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 410 30 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05265 Rev. *B
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised January 18, 2003
CY7C1357A CY7C1355A
Functional Block Diagram 256Kx36[1]
ZZ M O DE CEN A D V /LD WE WEN B W a, BWb B W c, BWd C E , CE1, CE2,CE3 A 0 , A1,, SA A A0 A1,
C o n tr o l
C o n t ro l Logic
M ux
C LK
OE
O u tp ut Buffers
D Q a-D Q d
Functional Block Diagram 512Kx18[1]
ZZ M OD E CEN A D V / LD R /W WEN B Wa , BWb C E, CE1, CE2,CE3 A0 , A1,SA A A0, A1, 512K x 9 x 2 SRAM Array
A d d re s s
Control
C ontro l Logic
M ux
C LK
OE
O utp ut Buffers
DQ a , D Qb
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05265 Rev. *B
DO S el
DI
In p u t R eg i s t ers
DO Sel
DI
In p u t R e g ist e rs
256K x 9 x 4 SRAM Array
A d d r e ss
Page 2 of 28
CY7C1357A CY7C1355A
Pin Configurations
100-pin TQFP Packages 256Kx36--CY7C1355A Top View
A A CE1 CE2 BWd BWc BWb BWa CE3 VCC VSS CLK WE N /WE CEN OE ADV/LD NC A A A
512Kx18--CY7C1357A Top View
A A CE1 CE2 NC NC BWb BWa CE3 VCC VSS CLK WE N /WE CEN OE ADV/LD NC A A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc VSS VCC VCC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS VSS VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb VSS VCC VCC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS VSS VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Document #: 38-05265 Rev. *B
MODE SA SA SA SA SA1 SA0 TMS TDI VSS VCC TDO TCK A A A A A A A
MODE A A A A A1 A0 TC NMS NTDI C VSS VCC TC NDO TC NCK A A A A A A A
Page 3 of 28
CY7C1357A CY7C1355A
Pin Configurations (continued)
119-ball Bump BGA 256Kx36--CY7C1355A Top View
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 NC ADV/LD VCC NC CE1 OE A WEN VCC CLK NC CEN A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS VSS A TDO 6 A CE3 A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
Document #: 38-05265 Rev. *B
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CY7C1357A CY7C1355A
Pin Descriptions (CY7C1355A)
256K × 36 TQFP Pins 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 93, 94, 95, 96 256K × 36 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 3T, 4T, 5T 5L 5G 3G 3L Name A0, A1, A Type Description
InputSynchronous Address Inputs: The address register is triggered by Synchronous a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and true chip enables. A0 and A1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. InputSynchronous Byte Write Enables: Each nine-bit byte has its own Synchronous active LOW byte write enable. On load write cycles (when WEN and ADV/LD are sampled LOW), the appropriate byte write signal (BWx) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when WEN is sampled HIGH. The appropriate byte(s) of data are written into the device one cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if always doing a write to the entire 36-bit word. InputSynchronous Clock Enable Input: When CEN is sampled HIGH, all Synchronous other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled HIGH on the device outputs is as if the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. InputRead Write: WEN signal is a synchronous input that identifies Synchronous whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD is a Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. InputClock Clock: This is the clock input to CY7C1355A. Except for OE, ZZ, and MODE, all timing references for the device are made with respect to the rising edge of CLK.
BWa, BWb, BWc, BWd
87
4M
CEN
88
4H
WEN
89
4K
CLK
98, 92
4E, 6B
CE1, CE3
InputSynchronous Active LOW Chip Enable: CE1 and CE3 are used with Synchronous CE2 to enable the CY7C1355A. CE1 or CE3 sampled HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be High-Z one clock cycle after chip deselect is initiated. InputSynchronous Active High Chip Enable: CE2 is used with CE1 and Synchronous CE3 to enable the chip. CE2 has inverted polarity but otherwise is identical to CE1 and CE3. Input Asynchronous Output Enable: OE must be LOW to read data. Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied LOW. InputAdvance/Load: ADV/LD is a synchronous input that is used to load Synchronous the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and WEN are ignored when ADV/LD is sampled HIGH. InputStatic Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input.
97
2B
CE2
86
4F
OE
85
4B
ADV/ LD
31
3R
MODE
64
7T
ZZ
InputSleep Enable: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC.
Document #: 38-05265 Rev. *B
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