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Details, datasheet, quote on part number:CY7C1355B-100BZC
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Datasheet text preview:
PRELIMINARY
CY7C1355B CY7C1357B
256Kx36/512Kx18 Flow-Through SRAM with NoBLTM Architecture
Features
· No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles · Pin-for-pin compatible with ZBT Architecture · Fast access times: 6.5 ns, 7.5 ns, and 8.5 ns · Fast clock speed: 133, 117, and 100 MHz -- 6.5 ns (for 133-MHz device) -- 7.5 ns (for 117-MHz device) -- 8.5 ns (for 100-MHz device) · Internally synchronized registered outputs eliminate the need to control OE · 3.3V 5% and +5% power supply · 3.3V or 2.5V I/O supply · Single R/W (READ/WRITE) control pin · Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications · Interleaved or linear four-word burst capability · Individual byte write (BWaBWd) control (may be tied LOW) · CEN pin to enable clock and suspend operations · Three chip enables for simple depth expansion · Automatic Power-down feature available using ZZ mode or CE deselect. · JTAG boundary scan for BGA and fBGA packages · Low profile 119-ball BGA, 165-ball fBGA, and 100-pin TQFP packages transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization with the No Bus Latency (NoBL) architecture. They integrate 262,144 x 36 and 524,288 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and read-write control (R/W). BWc and BWd apply to CY7C1355B only. There are three Chip Enable pins (CE, CE2, CE3) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated. The CY7C1355B and CY7C1357B have an on-chip two-bit burst counter. In the burst mode, the CY7C1355B and CY7C1357B provide up to four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH).
Functional Description
The CY7C1355B and CY7C1357B SRAMs are flow-through synchronous SRAMs designed to eliminate dead cycles when
Logic Block Diagram
CLK CE ADV/LD Ax CEN CE1 CE2 CE3 WE BWSx M ode CONTROL and WRITE LO G I C 256K X 36/ 512K X 18 MEMORY ARRAY D Data-In REG. Q
DQ x DQP x
CY7C1 355 AX DQ X DQPX BWSX
X = 17:0 X = a, b, c, d X = a, b, c, d X = a, b, c, d
CY7C1 357
X = 18:0 X = a, b X = a, b X = a, b
OE
Cypress Semiconductor Corporation Document #: 38-05117 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 16, 2002
PRELIMINARY
Selection Guide
7C1355B-133 7C1357B-133 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 250 30 7C1355B-117 7C1357B-117 7.5 220 30
CY7C1355B CY7C1357B
7C1355B-100 7C1357B-100 8.5 180 30
Unit ns mA mA
Pin Configurations
100-pin TQFP Package
A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A
DQPc DQc DQc VDDQ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS/DNU VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb DQb VDDQ VSS
CY7C1355B (256K x 36)
DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa
MODE A A A A A1 A0
E(288) E(144)
VSS VDD
Document #: 38-05117 Rev. **
E(72)
E(36)
A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 2 of 25
PRELIMINARY
Pin Configurations (continued)
100-pin TQFP Package
A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD E(18) A
CY7C1355B CY7C1357B
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS/DNU VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1357B (512K x 18)
MODE A A A A A1 A0
E(288) E(144)
E(72)
VSS VDD
Document #: 38-05117 Rev. **
E(36)
A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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PRELIMINARY
Pin Configurations (continued)
119-Ball BGA Pinout CY7C1355B (256K x 36)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQ c VDDQ DQ c DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
CY7C1355B CY7C1357B
2
A CE2 A DQPc DQc DQ c DQc DQ c VDD DQd DQd DQd DQd DQPd A E(72) TMS
3
A A A VSS VSS VSS BWSc VSS NC VSS BWSd VSS VSS VSS MODE A TDI
4
E(18) ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BW Sb VSS NC VSS BWSa VSS VSS VSS NC A TDO
6
A CE3 A DQPb DQ b DQb DQ b DQb VDD DQ a DQa DQ a DQa DQPa A E(36) NC
7
VDDQ NC NC DQ b DQb VDDQ DQb DQ b VDDQ DQa DQ a VDDQ DQ a DQa NC ZZ VDDQ
CY7C1355B (512K x 18)7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC E(72) VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS
3
A A A VSS VSS VSS BWSb VSS NC VSS VSS VSS VSS VSS MODE A TDI
4
E(18) ADV/LD VDD NC CE1 OE A WE VDD CLK NC CEN A1 A0 VDD E(36) TCK
5
A A A VSS VSS VSS VSS VSS NC VSS BWSa VSS VSS VSS NC A TDO
6
A CE3 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Document #: 38-05117 Rev. **
Page 4 of 25
PRELIMINARY
Pin Definitions
Pin Name A0 A1 A BWSa BWSb BWSc BWSd WE ADV/LD I/O Type InputSynchronous InputSynchronous Pin Description
CY7C1355B CY7C1357B
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DQPa, BWSb controls DQb and DQPb, BWSc controls DQc and DQPc, BWSd controls DQd and DQPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQaDQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWSa, DQPb is controlled by BWSb, DQPc is controlled by BWSc, and DQPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device, 3.3V. Ground for the device. Should be connected to ground of the system.
InputSynchronous InputSynchronous
CLK CE1 CE2 CE3 OE
Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous I/OSynchronous
DQa DQb DQc DQd
DQPa DQPb DQPc DQPd MODE
I/OSynchronous
Input Strap Pin
VDD VDDQ VSS TDO TDI TMS
Power Supply Ground
I/O Power Supply Power supply for the 3.3V or 2.5V I/O circuitry. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous
Document #: 38-05117 Rev. **
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