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Part: CY7C1360B-250BZC
Category:
Description: 256K X 36/512K X 18 Pipelined SRAM
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C1360B-250BZC datasheet File size : 207 kB
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Datasheet text preview:
PRELIMINARY
CY7C1360B CY7C1362B
256K x 36/512K x 18 Pipelined SRAM
Features
· Supports bus operation up to 250 MHz -- Available speed grades are 250, 200, and 166 MHz · Fully registered inputs and outputs for pipelined operation · Single 3.3V power supply · Supports 3.3V and 2.5V I/Os · Fast clock-to-output times -- 2.6ns (for 250-MHz device) -- 3.0ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) · User-selectable burst counter supporting IntelŪ PentiumŪ interleaved or linear burst sequences · Separate processor and controller address strobes · Synchronous self-timed writes · Asynchronous output enable · Single Cycle Chip Deselect · Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball fBGA · TQFP Available with 3-Chip Enable and 2-Chip Enable · IEEE 1149.1 JTAG-Compatible Boundary Scan · "ZZ" Sleep Mode option and Stop Clock option All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). The CY7C1360B and CY7C1362B support either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPCTM. The burst sequence is selected through the MODE pin (Pin 31 and ball R3 for the TQFP and BGA packages, respectively.) Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Select (BWa,b,c,d for 1360B and BWa,b for 1362B) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state.
Functional Description
The CY7C1360B and CY7C1362B are 3.3V, 256K x 36 and 512K x 18 synchronous-pipelined cache SRAM, respectively.
Logic Block Diagram
CLK CE A DV Ax
D Data-In REG. Q CLK OUTPUT REGISTERS and LOGIC
AX DQ X DQPX BWX
1360B A[17:0] DQa,b,c,d DQPa,b,c,d BWa,b,c,d
1362B A[18:0] DQa,b DQP a,b BWa,b
GW CE1 CE2 CE3 BWE BWx MO DE ADSP ADSC ZZ OE
CONTROL and WRITE LOGIC
256Kx3 6/ 512Kx1 8 MEMORY ARRAY
DQ x DQPx
Selection Table
CY7C1360B-250 CY7C1362B-250 Maximum Access Time Maximum Operating Current Commercial Maximum CMOS Standby Current Commercial 2.6 250 30 CY7C1360B-200 CY7C1362B-200 3.0 220 30 CY7C1360B-166 CY7C1362B-166 3.5 180 30 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05291 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 15, 2002
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables)
CY7C1360B CY7C1362B
A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1360B (256K X 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa
NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQPb NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1362B (512K x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 E(72) E(36) VSS VDD E(18) A A A A A A A A
Document #: 38-05291 Rev. *A
MODE A A A A A1 A0 E(72) E(36) VSS VDD E(18) A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 2 of 31
PRELIMINARY
Pin Configurations (continued)
100-pin TQFP (2 Chip Enables)
CY7C1360B CY7C1362B
A A CE1 CE2 BWd BWc BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1360B (256K X 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa
NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQPb NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1362B (512K x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0
NC NC VSS VDD NC NC A A A A A A A
Document #: 38-05291 Rev. *A
MODE A A A A A1 A0 NC NC VSS VDD NC NC NC A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 31
PRELIMINARY
Pin Configurations (continued)
119-ball BGA (2 Chip Enables with JTAG)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC TMS CY7C1360B (256K x 36) 3 4 5 A ADSP A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
CY7C1360B CY7C1362B
CY7C1362B (512K x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ 2 A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 Vdd NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPa NC DQa NC DQd VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Document #: 38-05291 Rev. *A
Page 4 of 31
PRELIMINARY
Pin Configurations (continued)
165-ball TQFP fBGA (3 Chip Enable with JTAG)
CY7C1360B (256K x 36)
CY7C1360B CY7C1362B
1 A B C D E F G H J K L M N P R
E(288) NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE
2
A A NC DQc DQc DQc DQc VSS DQd DQd DQd DQd NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A
11
NC E(144) DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E(18) A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
CY7C1362B (512K x 18)
1 A B C D E F G H J K L M N P R
E(288) NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
2
A A NC DQb DQb DQb DQb VSS NC NC NC NC NC E(72) E(36)
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
11
A E(144) DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E(18) A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document #: 38-05291 Rev. *A
Page 5 of 31
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
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