|
|
Part: CY7C1361A-133BGC
Category:
Description: 256K X 36/512K X 18 Synchronous Flow-thru Burst SRAM
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C1361A-133BGC datasheet File size : 207 kB
Request For quote: Find where to buy CY7C1361A-133BGC
Datasheet text preview:
CY7C1361A CY7C1363A
256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
Features
· · · · · · · · · · · · · · · · · · Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V 5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: A package version and two chip enables for BG and AJ package versions Address pipeline capability Address, data, and control registers Internally self-timed Write cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down feature available using ZZ mode or CE deselect. JTAG boundary scan for BG and AJ package version Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), burst control inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and global Write (GW). However, the CE2 chip enable input is only available for the TA package version. Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs (DQa and DQb) along with BWa and BWb (no BWc, BWd, DQc, and DQd). For the B and T package versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1361A and CY7C1363A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1361A and CY7C1363A SRAMs integrate 262,144 × 36 and 524,288 × 18 SRAM cells with advanced
Selection Guide
7C1361A-150 7C1363A-150 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.0 480 10 7C1361A-133 7C1363A-133 6.5 360 10 7C1361A-117 7C1363A-117 7.0 320 10 7C1361A-100 7C1363A-100 8.0 270 10 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05259 Rev. *A
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised June 19, 2002
CY7C1361A CY7C1363A
Functional Block Diagram256K × 36[1]
BY TE a WRITE
BWa BWE CLK
D
Q
BY TE b WRITE
BWb
D
Q
GW
B YT E c WRITE
BWc
D
Q
BY TE d WRITE
BWd
D
Q
byte d write byte c write Output Buffers byte b write byte a write DQ a,DQ b DQ c,DQ d
CE CE2
EN ABL E
D
Q
D
Q
[2]CE2
OE ZZ P ow er Down Logic Inpu t R e g ist e r
16
A DS P A A DS C CL R A DV A 1 -A 0 MODE B in ary C ounter & Logic
A d d re ss R e g ist e r 256K x 9 x 4 SRAM Array
O U T PU T RE GI STE R
D
Q
Functional Block Diagram--512K × 18[1]
BYTE b WRITE
BWb BWE
D
Q
BYTE a WRITE
BWa GW
D
Q
byte a write byte b write Output Buffers
CE CE2 CE2 ZZ OE ADSP Power Down Logic
ENABLE
D
Q
D
Q
Input Register
17
A ADSC
Address Register 512K x 9 x 2 SRAM Array
OUTPUT REGISTER
CLR ADV A1-A0 MODE Binary Counter & Logic
D
Q
DQa,DQb
Notes: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. 2. CE2 is for TA version only.
Document #: 38-05259 Rev. *A
Page 2 of 26
CY7C1361A CY7C1363A
Pin Configurations
A A CE CE2 BWd BWc BWb BWa CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
A A CE CE2 NC NC BWb BWa CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP A Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE CE2 NC NC BWb BWa A VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1363A 512Kx18 100-Pin TQFP
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP A Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE CE2 BWd BWc BWb BWa A VCC VSS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1361A 256K × 36 100-pin TQFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP AJ Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP AJ Version
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSS NC DPa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-05259 Rev. *A
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 26
CY7C1361A CY7C1363A
Pin Configurations (continued)
CY7C1361A 256K × 36 119-ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
CY7C1363A 512K × 18 119-ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQb NC VCCQ NC DQb VCCQ NC DQb VCCQ DQb NC NC NC VCCQ 2 A CE2 A NC DQb NC DQb NC VCC DQb NC DQb NC DQb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A CE2 A DQa NC DQa NC DQa VCC NC DQa NC DQa NC A A NC 7 VCCQ NC NC NC DQa VCCQ DQa NC VCCQ DQa NC VCCQ NC DQa NC ZZ VCCQ
Document #: 38-05259 Rev. *A
Page 4 of 26
CY7C1361A CY7C1363A
256K × 36 Pin Descriptions
X36 PBGA Pins X36 QFP Pins Pin Name A0 A1 A Type InputSynchronous Pin Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle.
4P 37 4N 36 2A, 3A, 5A, 6A, 3B, 5B, 35, 34, 33, 32, 100, 6B, 2C, 3C, 5C, 6C, 99, 82, 81, 44, 45, 2R, 6R, 3T, 4T, 5T 46, 47, 48, 49, 50 92 (AJ Version) 43 (A Version) 5L 5G 3G 3L 4M 93 94 95 96 87
BWa BWb BWc BWd BWE
InputSynchronous
Byte Write: A byte Write is LOW for a Write cycle and HIGH for a Read cycle. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte Write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, Write control, and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active HIGH input is used to enable the device. Chip Enable: This active LOW input is used to enable the device. Not available for BG and AJ package versions. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. Address Status Controller: This active LOW input causes the device to be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
InputSynchronous
4E 2B (not available for PBGA) 4F 4G
98 97 92 (for A version only) 86 83
CE CE2 CE2
InputSynchronous InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous
OE ADV
4A
84
ADSP
4B
85
ADSC
InputSynchronous
3R
31
MODE
InputStatic
7T
64
ZZ
InputSleep: This active HIGH input puts the device in Asynchronous low-power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect).
Document #: 38-05259 Rev. *A
Page 5 of 26
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
|
|
|
