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Details, datasheet, quote on part number:GVT71256T18
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327
CY7C1359A /GVT 71256T 18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
· · · · · · · · · · · · · · · · · · · Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V 5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs JTAG boundary scan Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low-profile JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN). Asynchronous inputs include the Burst Mode Control (MODE), the Output Enable (OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Data inputs are registered with Data Input Enable (DEN) and chip enable pins (CE, CE2, and CE2). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1DQ9. WEH controls DQ10DQ18. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The CY7C1359C/GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8 MB secondary cache.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
Selection Guide
7C1359A-166 71256T36-6 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 3.5 310 20 7C1359A-150 71256T36-6.7 3.8 275 20 7C1359A-133 71256T36-7.5 4.0 250 20 7C1359A-100 71256T36-10 4.5 190 20
Cypress Semiconductor Corporation Document #: 38-05120 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised September 13, 2001
CY7C1359A/GVT71256T18
Functional Block Diagram--256Kx18[1]
HIGHER BYTE WRITE
WEH# BWE#
D
Q
D
LOWER BYTE WRITE
Q
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# MOE# Power Down Logic Latch
D
Q
lo byte write hi byte write
ENABLE
D
Q
D
Q
D
Q
MATCH
Compare
DEN# Latch CLK A ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic 16 Address Register
Input Register
OUTPUT REGISTER
256K x 9 x 2 SRAM Array
Output Buffers
D
Q
DQ1DQ18
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05120 Rev. **
Page 2 of 24
CY7C1359A/GVT71256T18
Pin Configurations
100-Pin TQFP Top View
A A CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A NC NC NC VCCQ VSSQ NC NC DQ10 DQ11 VSSQ VCCQ DQ12 DQ13 NC V CC NC VSS DQ14 DQ15 VCCQ VSSQ DQ16 DQ17 DQ18 NC VSSQ VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1359A/GVT71256T18
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSSQ NC DQ9 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ MATCH DEN MOE
1 A B C D E F G H J K L M N P R T U Document #: 38-05120 Rev. ** VCCQ NC NC DQ10 NC VCCQ NC DQ13 VCCQ NC DQ15 VCCQ DQ17 NC NC NC VCCQ
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
119-Lead BGA Top View 2 A CE2 A NC DQ11 NC DQ12 NC VCC DQ14 NC DQ16 NC DQ18 A A TMS 3 A A A VSS VSS VSS WEH VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS WEL VSS VSS VSS NC A TDO 6 A CE2 A DQ9 NC DQ7 NC DQ5 VCC NC DQ3 MATCH DQ2 MOE A A NC 7 VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ DEN DQ1 NC ZZ VCCQ Page 3 of 24
CY7C1359A/GVT71256T18
Pin Descriptions
BGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 5L 3G TQFP Pins 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 93 94 Name A0 A1 A Type InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle.
WEL WEH
InputSynchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. WEL controls DQ1DQ9. WEH controls DQ10DQ18. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control, and data input enable control input on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active LOW input is used to enable the device. Chip Enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
4M
87
BWE
InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
InputSynchronous
4E 6B 2B 4F 4G
98 92 97 86 83
CE CE2 CE2 OE ADV
InputSynchronous InputSynchronous inputSynchronous Input InputSynchronous InputSynchronous InputSynchronous
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
InputStatic
7T
64
ZZ
InputSnooze: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). InputSynchronous Output Data Input Enable: This active LOW input is used to control the update of data input registers. Match Output: MATCH will be HIGH if data in the data input registers match the data stored in the memory array, assuming MOE being LOW. MATCH will be LOW if data do not match.
7N 6M
52 53
DEN MATCH
Document #: 38-05120 Rev. **
Page 4 of 24
CY7C1359A/GVT71256T18
Pin Descriptions (continued)
BGA Pins 6P 7P, 6N, 6L, 7K, 6H, 7G, 6F, 7E, 6D, 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 5U 2U 3U 4U 4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U TQFP Pins 51 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 42 38 39 43 15, 41,65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 Name MOE DQ1 DQ18 Type Input Input/ Output Description Match Output Enable: This active LOW asynchronous input enables the MATCH output drivers. Data Inputs/Outputs: Input data must meet setup and hold times around the rising edge of CLK.
TDO TMS TDI TCK VCC VSS
Output Input
IEEE 1149.1 test output. LVTTL-level output. IEEE 1149.1 test inputs. LVTTL-level inputs.
Supply Ground
Power Supply: +3.3V 5% and +10% Ground: GND
4, 11, 20, 27, 54, 61, 70, 77
VCCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to VCC)
1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16, 2D, 4D, 7D, 1E, 25, 28-30, 56, 57, 6E, 2F, 1G, 6G, 66, 75, 78, 79, 95, 2H, 7H, 3J, 5J, 96 1K, 6K, 2L, 4L, 7L, 2N, 1P, 1R, 5R, 7R, 1T, 4T, 6U
NC
-
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
Partial Truth Table for MATCH[2, 3, 4, 5, 6]
Operation READ Cycle WRITE Cycle Fill WRITE Cycle COMPARE Cycle Deselected Cycle (MATCH Out) Deselected Cycle E L L L L H H WE H L L H X X DEN X L H L X X MOE X X X L L H OE L H H H X X MATCH Output H High-Z DQ Q D High-Z D High-Z High-Z
Notes: 2. X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW. 3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW. 4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
Document #: 38-05120 Rev. **
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