|
Details, datasheet, quote on part number:GVT71512ZC18
| |
Datasheet text preview:
PRELIMINARY
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
256Kx36/512Kx18 Pipelined SRAM with NoBLTM Architecture
Features
· Zero Bus Latency, no dead cycles between write and read cycles · Fast clock speed: 200, 166, 133, and 100 MHz · Fast access time: 3.2, 3.6, 4.2, 5.0 ns · Internally synchronized registered outputs eliminate the need to control OE · Single 3.3V 5% and +5% power supply V CC · Separate V CCQ for 3.3V or 2.5V I/O · Single R/W (READ/WRITE) control pin · Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications · Interleaved or linear 4-word burst capability · Individual byte write (BWaBWd) control (may be tied LOW) · CKE pin to enable clock and suspend operations · Three chip enables for simple depth expansion · Snooze Mode for low power standby · JTAG boundary scan · Low profile 119-bump, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages Chip Enables (CE, CE2 and CE2), Cycle Start Input (ADV/LD), Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (R/W). BWc and BWd apply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either read or write. A clock enable (CKE) pin allows operation of the CY7C1354A/GVT71256ZC36/CY7C1356A/G VT71512ZC 18 to be suspended as long as necessary. All synchronous inputs are ignored when (CKE) is HIGH and the internal device registers will hold their previous values. There are three chip enable pins (CE, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state two cycles after chip is deselected or a write cycle is initiated. The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 have an on-chip 2-bit burst counter. In the burst mode, the CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD =LOW) or increment the internal burst counter (ADV/LD =HIGH) Output Enable (OE), Snooze Enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.
Functional Description
The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency (ZBL)/No Bus Latency (NoBL). They integrate 262,144x36 and 524,288x18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. These employ high-speed, low-power CMOS designs using advanced triplelayer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion
Selection Guide
7C1354A-200 71256ZC36-5 7C1356A-200 71512ZC18-5 M aximum Access Time (ns) M aximum Operating Current (mA) Com' l M aximum CMOS Standby Current (mA) Com'l 3.2 560 30 7C1354A-166 71256ZC36-6 7C1356A-166 71512ZC18-6 3.6 480 30 7C1354A-133 71256ZC36-7.5 7C1356A-133 71512ZC18-7.5 4. 2 410 30 7C1354A-100 71256ZC36-10 7C1356A-100 71512ZC18-10 5.0 350 30
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
·
3901 Nor th First Street
·
San Jose
·
C A 95134
·
408-943-2600 May 18, 2000
PRELIMINARY
.
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
Functional Block Diagram--256Kx36[1]
ZZ MODE CKE# ADV/LD# R/W# BWa#, BWb# BWc#, BWd# CE#, CE2#, CE2 SA0, SA1, SA 256K x 9 x 4 SRAM Array
Address
Control
Control Logic
Mux
CLK
Output Registers
OE#
Output Buffers
DQa-DQd
Functional Block Diagram--512Kx18[1]
ZZ MODE CKE# ADV/LD# R/W# BWa#, BWb# CE#, CE2#, CE2 SA0, SA1, SA 1M x 9 x 2 SRAM Array
Address
Control
Control Logic
Mux
CLK
Output Registers
OE#
Output Buffers
DQa, DQb
Note: 1. Th e Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2
DO Sel
DI
Input Registers
DO Sel
DI
Input Registers
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
SA SA CE C E2 BWd BWc BW b BW a C E2 VCC V SS CL K R /W CK E OE A D V /L D NC SA
SA SA CE CE 2 NC NC B Wb B Wa CE 2 V CC V SS C LK R /W C KE OE AD V/L D NC SA
D Qb DQb D Qb V CCQ VSS
SA SA
10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
D Qc DQ c DQ c VCCQ
VSS D Qc D Qc DQc DQc VSS VCCQ DQc DQc VCC VCC VCC VSS DQ d DQd VCCQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1354A/ GVT71256ZC36 (256K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC V CCQ VSS NC NC DQ b DQ b VSS VCCQ DQ b DQ b VCC V CC VCC VS S DQ b DQ b V CCQ VS S DQ b DQ b D Pb NC VSS VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
D Qb DQb DQb DQb VSS V DDQ DQb DQb VSS V CC V CC ZZ DQa DQa V CCQ VSS DQa DQa D Qa DQa VSS V CCQ DQ a D Qa DQa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SA NC NC V C CQ VSS NC DQ a DQ a DQa VSS V C CQ DQ a DQ a VSS VC C VC C ZZ DQ a DQ a V C CQ VSS DQ a DQ a NC NC VSS V C CQ NC NC NC
CY7C1356A/ GVT71512ZC18 (512K x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
M OD E SA SA SA SA SA 1 SA 0 T MS TDI V SS VC C
TDO TCK SA SA SA SA SA SA SA
MODE SA SA SA SA S A1 S A0 TM S TDI VS S VC C
TDO TCK SA SA SA SA SA SA
3
SA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PRELIMINARY
Pin Configurations (continued)
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
119-Ball Bump BGA CY7C1354A/GVT71256ZC 36 (256K x 36) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 SA CE2 SA DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd SA NC TM S 3 SA SA SA VSS VSS VSS B Wc VSS NC VSS B Wd VSS VSS VSS MO DE SA TDI 4 NC ADV/LD VCC NC CE OE SA R/W VCC CLK NC CKE SA1 SA0 VCC SA TCK 5 SA SA SA VSS VSS VSS BW b VSS NC VSS BWa VSS VSS VSS VSS SA TDO 6 SA CE2 SA DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa SA NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
CY7C1356A/GVT71512ZC 18 (512K x 18) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQb NC VCCQ NC DQb VCCQ NC DQb VCCQ DQb NC NC NC VCCQ 2 SA CE2 SA NC DQb NC DQb NC VCC DQb NC DQb NC DQb SA SA TMS 3 SA SA SA VSS VSS VSS BW b VSS NC VSS VSS VSS VSS VSS MODE SA T DI 4 NC ADV/LD VCC NC CE OE SA R/W VCC CLK NC CKE SA1 SA0 VC C NC TCK 5 SA SA SA VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS VCC SA T DO 6 SA CE2 SA DQ a NC DQ a NC DQ a VCC NC DQ a NC DQ a NC SA SA NC 7 VCCQ NC NC NC DQa VCCQ DQa NC VCCQ DQa NC VCCQ NC DQa NC ZZ VCCQ
4
PRELIMINARY
Pin Descriptions--256Kx36
256Kx36 TQFP Pins 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 93, 94, 95, 96 256Kx36 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 3T, 4T, 5T 5L 5G 3G 3L N a me SA0, SA1, SA Type InputSynchronous
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
Description Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD LOW, CKE LOW and true chip enables. SA0 and SA1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. Synchronous Byte Write Enables: Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W# and ADV/LD are sampled LOW), the appropriate byte write signal (BWx) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when R/W is sampled HIGH. The appropriate byte(s) of data are written into the device two cycles later. BWa controls DQa pins; BWb controls DQb pins; BWc controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if always doing write to the entire 36-bit word. Synchronous Clock Enable Input: When CKE is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CKE sampled HIGH on the device outputs is as if the LOW-to-HIGH clock transition did not occur. For normal operation, CKE must be sampled LOW at rising edge of clock. Read Write: R/W signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD is a Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later. Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Except for OE, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. Synchronous Active LOW Chip Enable: CE and CE2 are used with CE2 to enable the CY7C1354A/GVT71256ZC36. CE or CE2 sampled HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be High-Z two clock cycles after chip deselect is initiated. Synchronous Active High Chip enable: CE2 is used with CE and CE2 to enable the chip. CE2 has inverted polarity but otherwise is identical to CE and CE2. Asynchronous Output Enable: OE must be LOW to read data. When OE is HIGH, the I/O pins are in high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied LOW. Advance/Load: ADV/LD is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and R/W are ignored when ADV/LD is sampled HIGH. Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input.
BWa, BWb, BWc, BWd
InputSynchronous
87
4M
CKE
InputSynchronous
88
4H
R/W
InputSynchronous
89
4K
CLK
InputSynchronous InputSynchronous
98, 92
4E, 6B
CE, CE2
97
2B
CE2
InputSynchronous Input
86
4F
OE
85
4B
ADV/LD
InputSynchronous
31
3R
MOD E
InputStatic
5
|
|
