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Details, datasheet, quote on part number:GVT7164B18
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Datasheet text preview:
297A
CY7C1297A/ GVT7164 B18
64K X 18 Synchronous Burst SRAM
Features
· · · · · · · · · · · · · · · · · Fast access times: 9 and 10 ns Fast clock speed: 66 and 50 MHz Provide high performance 2-1-1-1 access rate Fast OE access times: 5 and 6 ns Single +3.3V 5% and +10% power supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages Low-capacitive bus loading High 30-pF output drive capability at rated access time The CY7C1297A/GVT7164B18 SRAM integrates 65536 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE), Burst Mode Control (MODE), and Sleep Mode Control (ZZ). The data outputs (DQ), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and Read controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one or two bytes wide as controlled by the Read control inputs. Individual byte enables allow individual bytes to be written. WEL controls DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The CY7C1297A/GVT7164B18 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, 680 × 0, and PowerPCTM systems and for systems that benefit from a wide synchronous data bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
Selection Guide
7C1297A-66 7164B18-9 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 9.0 240 2 7C1297A-50 7164B18-10 10.0 240 2 7C1297A1-50 7164B18-12 10.0 240 2 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05204 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised January 22, 2002
CY7C1297A/ GVT7164B18
Functional Block Diagram--64Kx18[1]
UPPER BYTE WRITE
WEH# BWE# CLK
D
Q
LOWER BYTE WRITE
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# Power-down Logic
D
Q
lo byte write hi byte write Output Buffers
ENABLE
D
Q
Input Register
A15-A2 ADSC#
Address Register 128K x 9 x 2 SRAM Array
CLR ADV# A1-A0 MODE Binary Counter and Logic
DQ1-DQ16 DQP1 DQP2
Note: 1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05204 Rev. **
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CY7C1297A/ GVT7164B18
Pin Configuration
100-pin TQFP Top View
A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 NC NC NC V CCQ VSSQ NC NC DQ9 DQ10 VSSQ V CCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 V CCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ V CCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1297A/GVT7164B18
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A 10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC
Pin Descriptions
QFP Pins 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44 93, 94 Pin Name A0A16 Type Description InputAddresses: These inputs are registered and must meet the set-up and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycles. InputByte Write Enables: A byte Read enable is LOW for a Write cycle and HIGH Synchronous for a Read cycle. WEL controls DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and DQP2. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE LOW. InputWrite Enable: This active LOW input gates byte Read operations and must Synchronous meet the set-up and hold times around the rising edge of CLK. InputGlobal Write: This active LOW input allows a full 18-bit Write to occur Synchronous independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. InputClock: This signal registers the addresses, data, chip enables, Write control Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. InputChip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP. InputChip Enable: This active LOW input is used to enable the device. Synchronous InputChip Enable: This active HIGH input is used to enable the device. Synchronous Page 3 of 12
WEL, WEH
87 88
BWE GW
89
CLK
98 92 97
CE CE2 CE2
Document #: 38-05204 Rev. **
MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CY7C1297A/ GVT7164B18
Pin Descriptions (continued)
QFP Pins 86 83 Pin Name OE ADV Type Input Description Output Enable: This active LOW asynchronous input enables the data output drivers.
InputAddress Advance: This active LOW input is used to control the internal Synchronous burst counter. A HIGH on this pin generates wait cycle (no address advance). InputAddress Status Processor: This active LOW input, along with CE being Synchronous LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. InputAddress Status Controller: This active LOW input causes device to be Synchronous deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
84
ADSP
85
ADSC
31 64
MODE ZZ
InputSnooze: This active HIGH input puts the device in low power consumption Asynchronous standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Input/ Output Input/ Output Supply Ground I/O Supply I/O Ground Data Inputs/Outputs: Low Byte is DQ1DQ8. High Byte is DQ9DQ16. Input data must meet set-up and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1DQ8 and DQP2 is parity bit for DQ9DQ16. Power Supply: +3.3V 5% and +10% Ground: GND. Output Buffer Supply: +2.375 to 3.6V Output Buffer Ground: GND No Connect: These signals are not internally connected.
58, 59, 62, 63, 68, DQ1DQ16 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 74, 24 15, 41, 65, 91 14, 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 13, 6, 7, 14, 16, 25, 2830, 38, 39, 42, 43, 4953, 56, 57, 66, 75, 78, 79, 80, 95, 96 DQP1, DQP2 VCC VSS VCCQ VSSQ NC
Burst Address Table (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
Document #: 38-05204 Rev. **
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CY7C1297A/ GVT7164B18
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 ADSP X X H X H L L L L L X X X X X X X X X X X X X L X L X H H H H H X X X X X X X X X X X X X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X CLK LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH LH DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Partial Truth Table for Read/Write
Function Read Read Write one byte Write all bytes Write all bytes GW H H H H L BWE H L L L X WEH X H L L X WEL X H H L X
Notes: 2. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. 3. WEL enables Write to DQ1DQ8 and DQP1. WEH enables Write to DQ9DQ16 and DQP2. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a Read cycle at the LH edge of CLK. A Write cycle can be performed by setting WRITE LOW for the CLK LH edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05204 Rev. **
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