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Details, datasheet, quote on part number:GVT7164T18-7
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Datasheet text preview:
327
CY7C1358A / GVT 7164T 18
64K x 18 Synchronous Cache Tag RAM Pipelined Output
Features
· · · · · · · · · · · · · · Fast match times: 4.5, 5.0, 6.0, and 7.0 ns Fast clock speed: 133, 100, 83, and 75 MHz Fast OE access times: 4.5 ns and 5.0 ns Pipelined data comparator Data input register load control by DEN 3.3V 5% and +10% power supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Two chip enables for depth expansion Address, data, and control registers Internally self-timed Write cycle Automatic power-down for portable applications Low profile 100-pin TQFP package
Functional Description
The Cypress Synchronous SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT7164T18 SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a 18-bit comparator for tag compare operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE and CE1), Write Enable (WE), and Data Input Enable (DEN). Asynchronous inputs include the Output Enable (OE) and the Match Output Enable (MOE). The Data Outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous. Data inputs are registered with Data Input Enable (DEN) and Chip Enable pins (CE, CE1). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK). The GVT7164T18 operates from a +3.3V power supply. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 2 MB secondary cache.
Selection Guide
7C1358A-133 7164T18-4 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 4.5 300 20 7C1358A-100 7164T18-5 5.0 240 20 7C1358A-83 7164T18-6 6.0 220 20 7C1358A-75 7164T18-7 7.0 200 20
Cypress Semiconductor Corporation Document #: 38-05121 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised September 13, 2001
CY7C1358A/ GVT7164T18
Functional Block Diagram--64Kx18[1]
WRITE
WE#
D
Q
D
Q
OE# MATCH MOE#
D
Q
CE# CE1 Latch
ENABLE
D
Q
Compare
DEN# 16
Input Register Latch
A CLK
Address Register 64K x 9 x 2 SRAM Array
OUTPUT REGISTER
Output Buffers
D
Q
DQ1DQ18
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05121 Rev. **
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CY7C1358A/ GVT7164T18
Pin Configurations
100-Pin TQFP Top View
A A CE CE1 NC NC NC NC NC VCC VSS CLK NC WE OE NC NC NC A A NC NC NC VCC VSS NC NC DQ10 DQ11 VSS VCC DQ12 DQ13 NC VCC NC VSS DQ14 DQ15 VCC VSS DQ16 DQ17 DQ18 NC VSS VCC NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1358A/GVT7164T18
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCC VSS NC DQ9 DQ8 DQ7 VSS VCC DQ6 DQ5 VSS NC VCC NC DQ4 DQ3 VCC VSS DQ2 DQ1 NC NC VSS VCC NC NC NC
1 A B C D E F G H J K L M N P R T U Document #: 38-05121 Rev. ** VCC NC NC DQ10 NC VCC NC DQ13 VCC NC DQ15 VCC DQ17 NC NC NC VCC
2 A CE1 NC NC DQ11 NC DQ12 NC VCC DQ14 NC DQ16 NC DQ18 A A DEN
NC A A A A A A VSS MATCH VSS VCC DEN MOE A A A A A NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
119-Lead BGA Top View 3 A NCA NC VSS VSS VSS NC VSS NC VSS VSS VSS VSS VSS A A NC 4 NC NC VCC NC NC OE NC WE VCC CLK NC NC A A VCC MATCH A 5 A NC A VSS VSS VSS VSS VSS NC VSS NC VSS VSS VSS A A MOE 6 NC CE A DQ9 NC DQ7 NC DQ5 VCC NC DQ3 NC DQ2 NC A A NC 7 VCC NC NC NC DQ8 VCC DQ6 NC VCC DQ4 NC VCC NC DQ1 NC ZZ VCC Page3 of 11
CY7C1358A/ GVT7164T18
Pin Descriptions
BGA Pins 2A, 3A, 5A, 5C, 6C, 4N, 4P, 2R, 3R, 5R, 6R, 2T, 3T, 5T, 6T, 4U 4H TQFP Pins 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44 87 Pin Name A Type InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK.
WE
InputSynchronous InputSynchronous
Write Enable: this write enable is LOW for a Write cycle and HIGH for a Read cycle. Data I/O are high impedance one cycle after WE = LOW is gated into register. Clock: This signal registers the addresses, data, chip enables, write control and data input enable control input on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device. Chip Enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Data Input Enable: This active LOW input is used to control the update of data input registers. Match Output: MATCH will be HIGH if data in the data input registers match the data stored in the memory array, assuming MOE being LOW. MATCH will be LOW if data do not match. Match Output Enable: This active LOW asynchronous input enables the MATCH output drivers. Data Inputs/Outputs: Input data must meet set-up and hold times around the rising edge of CLK.
4K
89
CLK
6B 2B 4F 2U 4T
98 97 86 42 39
CE CE1 OE DEN MATCH
InputSynchronous InputSynchronous Input InputSynchronous Output
5U 7P, 6N, 6L, 7K, 6H, 7G, 6F, 7E, 6D, 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 1A, 7A, 4C, 1F, 7F, 1J, 2J, 4J, 6J, 7J, 1M, 7M, 4R, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 4A, 6A, 1B, 3B, 4B, 5B, 7B, 1C, 2C, 3C, 7C, 2D, 4D, 7D, 1E, 4E, 6E, 2F, 1G, 3G, 4G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 5L, 7L, 4M, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 7T, 3U, 6U
43 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 5, 10, 17, 21, 26, 38, 40, 55, 60, 67, 71, 76, 90
MOE DQ1 DQ18
Input Input/ Output
VCC
Supply
Power Supply: +3.3V 5% and +10%
VSS
Ground
Ground: GND
1-3, 6, 7, 14, 16, 25, 28-31, 49-53, 56, 57, 64, 66, 75, 78, 79, 83-85, 88, 92-96
NC
-
No Connect: These signals are not internally connected.
Document #: 38-05121 Rev. **
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CY7C1358A/ GVT7164T18
Truth Table[2, 3, 4, 5, 6]
Operation READ Cycle WRITE Cycle Fill WRITE Cycle COMPARE Cycle Deselected Cycle (MATCH Out) Deselected Cycle E L L L L H H WE H L L H X X DEN X L H L X X MOE X X X L L H OE L H H H X X MATCH Output H High-Z DQ Q D High-Z D High-Z High-Z
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... 0.5V to +4.6V VIN ..0.5V to VCC+0.5V Storage Temperature (plastic) ........... 55°C to +150°C Junction Temperature ..... +150°C
Power Dissipation.......... 1.0W Short Circuit Output Current....... 50 mA
Operating Range
Range Com'l Ambient Temperature[7] 0°C to +70°C VCC 3.3V -5%/+10%
Notes: 2. X means "Don't Care." H means logic HIGH. L means logic LOW. 3. E=L is defined as CE = LOW and CE1 = HIGH. E =H is defined as CE=HIGH or CE1 = LOW. 4. All inputs except OE and MOE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 7. TA is the case temperature.
Document #: 38-05121 Rev. **
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