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Details, datasheet, quote on part number:W144H
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| Part: | W144H |
| Category: | Timing Circuits => Clock Generators => Motherboard |
| Description: | 440BX Agpset Spread Spectrum Frequency Synthesizer |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W144H datasheet File size : 159 kB |
| Request For quote: | Find where to buy W144H
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Datasheet text preview:
PRELIMINARY
W144
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
· Maximized EMI suppression using Cypress's Spread Spectrum technology · Single chip system frequency synthesizer for Intel® 440BX AGPset · Two copies of CPU output · Six copies of PCI output · One 48-MHz output for USB · One 24-MHz output for SIO · Two buffered reference outputs · One IOAPIC output · Thirteen SDRAM outputs provide support for 3 DIMMs · Supports frequencies up to 150 MHz · I2CTM interface for programming · Power management control inputs Table 1. Mode Input Table Mode 0 1 PCI_STOP# REF0 Pin2
Table 2. Pin Selectable Frequency FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Input Address CPU_F, CPU1 F S2 FS1 F S0 (MHz) PCI_F, 1:5 (MHz) 1 1 1 133.3 33.3 (CPU/4) 1 1 0 124 31 (CPU/4) 1 0 1 150 37.5 (CPU/4) 1 0 0 140 35 (CPU/4) 0 1 1 105 35 (CPU/3) 0 1 0 110 36.7 (CPU/3) 0 0 1 115 38.3 (CPU/3) 0 0 0 120 40 (CPU/3) 1 1 1 100 33.3 (CPU/3) 1 1 0 133.3 44.43 (CPU/3) 1 0 1 112 37.3 (CPU/3) 1 0 0 103 34.3 (CPU/3) 0 1 1 66.8 33.4 (CPU/2) 0 1 0 83.3 41.7 (CPU/2) 0 0 1 75 37.5 (CPU/2) 0 0 0 124 41.3 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: ........ 250 ps CPU to CPU Output Skew: ....... 175 ps PCI to PCI Output Skew: ........... 500 ps VDDQ3: ........... 3.3V±5% VDDQ2: ........... 2.5V±5% SDRAMIN to SDRAM0:11 Delay: ..3.7 ns typ. SDRAM0:11 (leads) to SDRAM_F Skew: .....0.4 ns typ.
Logic Block Diagram
VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration
REF1/FS2 VDDQ2 IOAPIC VDDQ2
I/O Pin Control
Stop Clock Control
CLK_STOP#
PLL 1
÷2,3,4
Stop Clock Control
CPU1 CPU_F VDDQ3 PCI_F/MODE PCI1/FS3 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS0
÷2
Stop Clock Control
SDATA SCLK
I2C Logic PLL2
VDDQ3 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI1/FS3 GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND 2 SDATA IC SCLK
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ2 IOAPIC REF1/FS2* GND CPU_F CPU1 VDDQ2 CLK_STOP# SDRAM_F GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0* 24MHz/FS1*
SDRAMIN
Stop Clock Control
24MHz/FS1 VDDQ3 SDRAM0:11 12 SDRAM_F
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull down resistor.
W144
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation Document #: 38-07153 Rev. *A
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised December 14, 02
PRELIMINARY
Pin Definitions
Pin Name CPU_F CPU1 PCI2:5 PCI1/FS3 Pin No. 44 43 10, 11, 12, 13 8 Pin Type O O O I/O
W144
PCI_F/MODE
7
I/O
CLK_STOP#
41
I
IOAPIC 48MHz/FS0
47 26
O I/O
24MHz/FS1
25
I/O
REF1/FS2
46
I/O
REF0/ (PCI_STOP#)
2
I/O
SDRAMIN SDRAM0:11
15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 40 24 23 4
I O
Pin Description Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Tables 2 and 6 for detailed frequency information. CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When an input, sets function of pin 2. CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after completing a full clock cycle (23 CPU clock latency). When brought HIGH, affected clock outputs start, beginning with a full clock cycle (23 CPU clock latency). IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW. 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 2. 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 2. I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which will set clock frequencies as described in Table 2. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:11, SDRAM_F). Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN input which is not affected by the CLK_STOP# input Clock pin for I2C Circuitry Data pin for I2C Circuitry Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
SDRAM_F SCLK SDATA X1
O I I/O I
X2 VDDQ3
5 1, 6, 14, 19, 27, 30, 36 42, 48 3, 9, 16, 22, 33, 39, 45
I P
VDDQ2 GND
P G
Document #: 38-07153 Rev. *A
Page 2 of 15
PRELIMINARY
Overview
The W144 was developed as a single-chip device to meet the clocking needs of the Intel 440BX AGPset. In addition to the typical outputs provided by standard 100-MHz 440BX FTGs, the W144 adds a thirteen output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them.
W144
Upon W144 power up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pin and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs are <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor Clock Load
Functional Description
I/O Pin Operation Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
10 k (Load Option 1) W144 Power-on Reset Timer Output Buffer Output Three-state
Q
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options Output Strapping Resistor Series Termination Resistor 10 k W144 Power-on Reset Timer Output Buffer Output Three-state
Q
VDD
R Resistor Value R
Clock Load
Hold Output Low
D
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07153 Rev. *A
Page 3 of 15
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