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Details, datasheet, quote on part number:W150
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| Part: | W150 |
| Category: | Timing Circuits => Clock Circuits |
| Description: | 440BX Agpset Spread Spectrum Frequency Synthesizer |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W150 datasheet File size : 183 kB |
| Request For quote: | Find where to buy W150
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Datasheet text preview:
PRELIMINARY
W150
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
· Maximized EMI suppression using Cypress's Spread Spectrum technology · Single chip system frequency synthesizer for Intel® 440BX AGPset · Three copies of CPU output · Seven copies of PCI output · One 48-MHz output for USB / One 24-MHz for SIO · Two buffered reference outputs · Two IOAPIC outputs · 17 SDRAM outputs provide support for 4 DIMMs · Supports frequencies up to 150 MHz · SMBus interface for programming · Power management control inputs Table 1. Mode Input Table. Mode 0 1 Table 2. Pin Selectable Frequency. Input Address FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
[1]
Pin 3 PCI_STOP# REF0
FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
CPU_F, 1:2 (MHz) 133.3 124 150 140 105 110 115 120 100 133.3 112 103 66.8 83.3 75 124
PCI_F, 0:5 (MHz) 33.3 (CPU/4) 31 (CPU/4) 37.5 (CPU/4) 35 (CPU/4) 35 (CPU/3) 36.7 (CPU/3) 38.3 (CPU/3) 40 (CPU/3) 33.3 (CPU/3) 44.43 (CPU/3) 37.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 37.5 (CPU/2) 41.3 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: ........ 250 ps CPU to CPU Output Skew: ....... 175 ps PCI to PCI Output Skew: ........... 500 ps SDRAMIN to SDRAM0:15 Delay: ..3.7 ns typ. VDDQ3: ........... 3.3V±5% VDDQ2: ........... 2.5V±5% SDRAM0:15 (leads) to SDRAM_F Skew: .....0.4 ns typ.
Logic Block Diagram
VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC PLL Ref Freq I/O Pin Control
CLK_STOP#
Pin Configuration
REF1/FS2
Stop Clock Control
VDDQ2 IOAPIC_F IOAPIC0 VDDQ2 CPU_F
PLL 1
÷2,3,4
Stop Clock Control
CPU1 CPU2 VDDQ3 PCI_F/MODE PCI0/FS3 PCI1 PCI2 PCI3
Stop Clock Control SDATA SCLK SMBus Logic
PCI4 PCI5 VDDQ3
VDDQ3 REF1/FS2 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI0/FS3 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 SDRAMIN SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDDQ2 IOAPIC0 IOAPIC_F GND CPU_F CPU1 VDDQ2 CPU2 GND CLK_STOP# SDRAM_F VDDQ3 SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDDQ3 24MHz/FS0 48MHz/FS1
W150
PLL2
Stop Clock Control
48MHz/FS1 24MHz/FS0 VDDQ3 SDRAM0:15 16 SDRAM_F
SDRAMIN
Note: 1. 1.Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation Document #: 38-07177 Rev. **
·
3901 North First Street
·
San Jose
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CA 95134 · 408-943-2600 Revised September 25, 2001
PRELIMINARY
Pin Definitions
Pin Name CPU1 :2 Pin No. 51, 49
W150
CPU_F
52
PCI1:5 PCI0/FS3
11, 12, 13, 14, 16 9
PCI_F/MODE
8
CLK_STOP#
47
IOAPIC_F
54
IOAPIC0 48MHz/FS1
55 29
24MHz/FS0
30
REF1/FS2 REF0 (PCI_STOP#)
2 3
SDRAMIN SDRAM0:15
17 44, 43, 41, 40, 39, 38, 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 46 28 27 5
Pin Type Pin Description O CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input. O Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input. O PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input. I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input. When an input, selects function of pin 3 as described in Table 1. I CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after completing a full clock cycle (23 CPU clock latency). When brought HIGH, affected outputs start beginning with a full clock cycle (23 CPU clock latency). O Free-running IOAPIC Output: This output is a buffered version of the reference input which is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied to VDDQ2. I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW. I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be latched, setting output frequencies as described in Table 2. I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched, setting output frequencies as described in Table 2. I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input will be latched, setting output frequencies as described in Table 2. I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz). I Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs (SDRAM0:15, SDRAM_F). Buffered Outputs: These sixteen dedicated outputs provide copies of the signal proO vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. O I I/O I Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318 MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected.
SDRAM_F SCLK SDATA X1
X2
6
I
Document #: 38-07177 Rev. **
Page 2 of 17
PRELIMINARY
Pin Definitions (continued)
Pin Name VDDQ3 Pin No. 1, 7, 15, 20, 31, 37, 45 50, 56 4, 10, 23, 26, 34, 42, 48, 53
W150
VDDQ2 GND
Pin Type Pin Description P Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz/24-MHz output buffers. Connect to 3.3V. P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. G Ground Connections: Connect all ground pins to the common system ground plane. tor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (<40, nominal) is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to minimize system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the corresponding specified output frequency is delivered on the pins, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor Clock Load Output Buffer Output Three-state
Q
Overview
The W150 was designed as a single-chip alternative to the standard two-chip Intel 440BX AGPset clock solution. It provides sufficient outputs to support most single-processor, four SDRAM DIMM designs.
Functional Description
I/O Pin Operation Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W150 power-up, the first 2 ms of operation are used for input logic selection. During this period, the five I/O pins (2, 8, 9, 29, 30) are three-stated, allowing the output strapping resis-
10 k (Load Option 1) W150 Power-on Reset Timer
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option.
Document #: 38-07177 Rev. **
Page 3 of 17
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