Details, datasheet, quote on part number: W181-03G
CategoryTiming Circuits => EMI Reduction
TitleEMI Reduction
DescriptionEmi Suppression
CompanyCypress Semiconductor Corp.
DatasheetDownload W181-03G datasheet
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Features, Applications


Cypress PREMISTM family offering Generates an EMI optimized clocking signal at the output Selectable input to output frequency Single or 3.75% down or center spread output Integrated loop filter components Operates with or 5V supply Low power CMOS design Available in 8-pin SOIC (Small Outline Integrated Circuit) or 14-pin TSSOP (Thin Shrink Small Outline Package select options only) Table 1. Modulation Width Selection SS% 02, 03 Output Fin Fout Fin ­ 1.25% Fin Fout Fin 52, 53 Output Fin + 0.625% Fin ­ 0.625% Fin + 1.875% Fin ­1.875%

Supply Voltages:...........................................VDD 3.3Vą5% or VDD = 5Vą10% Frequency Range:............................ 28 MHz Fin 75 MHz Crystal Reference Range.................. 28 MHz Fin 40 MHz Cycle to Cycle Jitter:....................................... 300 ps (max.) Selectable Spread or 3.75% Output Duty Cycle:............................... 40/60% (worst case) Output Rise and Fall Time:.................................. 5 ns (max.)

TSSOP FS2 CLKIN or X1 Oscillator or Reference Input or X2 GND NC SS% FS1 NC VDD NC CLKOUT

Pin Name CLKOUT CLKIN or X1 Pin No. (SOIC) 5 1 Pin No. 8 2 Pin Type O I Pin Description Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (SSON# asserted). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, to an external reference clock. Crystal Connection: If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. Power Connection: Connected or 5V power supply. Ground Connection: Connect all ground pins to the common system ground plane. No Connection.

The W181 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a lowfrequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. times the reference frequency. (Note: For the W181 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage is set or 3.75% (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common.

The W181 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q

Clock Input Freq. Divider Q Phase Detector Charge Pump


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