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Details, datasheet, quote on part number:W182-5G
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Datasheet text preview:
W182
Full Feature Peak Reducing EMI Solution
Features
· Cypress PREMISTM family offering · Generates an EMI optimized clocking signal at the output · Selectable output frequency range · Single 1.25% or 3.75% down or center spread output · Integrated loop filter components · Operates with a 3.3 or 5V supply · Low power CMOS design · Available in 14-pin SOIC (Small Outline Integrated Circuit) Table 1. Modulation Width Selection SS% 0 1 W182 Output Fin Fout Fin 1.25% Fin Fout Fin 3.75% W182-5 Output Fin + 0.625% Fin 0.625% Fin + 1.875% Fin 1.875%
Table 2. Frequency Range Selection FS2 0 0 1 1 F S1 0 1 0 1 Frequency Range 8 MHz FIN 10 MHz 10 MHz FIN 15 MHz 15 MHz FIN 18 MHz 18 MHz FIN 28 MHz
Key Specifications
Supply Voltages: .......... VDD = 3.3Vą5% or VDD = 5Vą10% Frequency Range: ...... 8 MHz Fin 28 MHz Cycle to Cycle Jitter: ....... 300 ps (max.) Selectable Spread Percentage: ...........1.25% or 3.75% Output Duty Cycle: ....... 40/60% (worst case) Output Rise and Fall Time: .......... 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC FS2 CLKIN or X1 NC or X2 GND GND SS% FS1 1 2 3 4 5 6 14 13 12 11 10 9 8 REFOUT OE# SSON# R e set VDD VDD CLKOUT
W 182/ W 182-5
X1 XTAL Input
X2
W182
Spread Spectrum Output (EMI suppressed)
7
3.3V or 5.0V
Oscillator or Reference Input
W182
Spread Spectrum O ut put (EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation Document #: 38-07151 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised September 24, 2001
W182
Pin Definitions
Pin Name CLKOUT REFOUT Pin No. 8 14 Pin Type O O Pin Description Output Modulated Frequency: Frequency modulated copy of the input clock (SSON# asserted). Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. Output Enable (Active LOW): When this pin is held HIGH, the output buffers are placed in a high-impedance mode.This pin has an internal pull-down resistor. Modulation Profile Restart: A rising edge on this input restarts the modulation pattern at the beginning of its defined path. This pin has an internal pull-down resistor. Frequency Selection Bit(s): These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common ground plane.
CLKIN or X1
2
I
NC or X2 SSON#
3 12
I I
SS%
6
I
OE#
13
I
Reset
11
I
FS1:2 VDD GND
7, 1 9,10 4,5
I P G
Document #: 38-07151 Rev. *A
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W182
Overview
The W182 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. times the reference frequency. (Note: For the W182 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pin SS% as shown in Table 1. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided.
Functional Description
The W182 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q
VD D
Clock Input Freq. Divider Q Phase Detector Charge Pump
Reference Input
VCO
Post Dividers
CL KOUT (EMI suppressed)
Modulating Waveform Feedback Divider P
PLL
GND
Figure 1. Functional Block Diagram
Document #: 38-07151 Rev. *A
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