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Details, datasheet, quote on part number:W204
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Datasheet text preview:
PRELIMINARY
W204
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
ˇ Maximized EMI suppression using Cypress's spread spectrum technology ˇ Optimized system frequency synthesizer for 440BX and VIA Apollo Pro-133 ˇ Four copies of CPU output ˇ Eight copies of PCI clock (synchronous w/CPU output) ˇ Two copies of 14.318-MHz IOAPIC output and three buffered copies of 14.318-MHz reference input ˇ One copy of 48-MHz USB output ˇ Selectable 24-/48-MHz clock-through-resistor strapping ˇ Power management control input pins ˇ Programmable clock outputs up to 155 MHz via SMBus interface (32 selectable frequencies) CPU Cycle to Cycle Jitter: .........250 ps CPU0:3 Output Skew: ......175 ps PCI_F, PCI1:7 Output Skew: ...... 500 ps CPU to PCI Output Skew: ...... 1.04.0 ns (CPU Leads) REF0/SEL48#, SCLK,SDATA:... 250K pull-up FS1: ...... 250K pull-down FS0: ......... No pull-up or pull-down Test mode and output three-state through SMBus interface Table 1. Pin Selectable Frequency FS1 1 1 0 0 Supply Voltages: .... VDDQ3 = 3.3Vą5% VDDQ2 = 2.5Vą5% FS0 1 0 1 0 CPU(0:3) 133.3 MHz 105 MHz 100 MHz 66.8 MHz PCI 33.3 MHz 35 MHz 33.3 MHz 33.3 MHz
Key Specifications
Block Diagram
VDDQ3 REF0/SEL48# X1 X2 XTAL OSC PLL Ref Freq VDDCORE0/1 GNDCORE0/1 REF1 REF2 GND VDDQ2 APIC0 APIC1 GND VDDQ2 CPU0 Stop Clock Control FS0:1 PLL 1 ÷2/÷3 SPREAD# CPU1 GND VDDQ2 CPU2 CPU3 GND VDDQ3 PCI_F Stop Clock Control PCI_STOP# PCI1 PCI2 PCI3 GND VDDQ3 PCI4 I2C Logic Power Down Control PLL2 PCI5 PCI6 PCI7 PWR_DWN# GND VDDQ3 48MHz 24_48MHz/FS1 GND
Pin Configuration
REF0/SEL48# REF1 GND X1 X2 GND PCI_F PCI1 V DDQ3 PCI2 PCI3 GND PCI4 PCI5 V DDQ3 PCI6 PCI7 GND V DDQ3 GND V DDQ3 48MHz 24_48MHz/FS1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
[1]
CPU_STOP#
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ3 REF2 VDDQ2 APIC0 APIC1 GND NC VDDQ2 CPU0 CPU1 GND VDDQ2 CPU2 CPU3 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SDATA SCLK FS0
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH.
SDATA SCLK
Cypress Semiconductor Corporation Document #: 38-07264 Rev. **
ˇ
3901 North First Street
ˇ
San Jose
ˇ
CA 95134 ˇ 408-943-2600 Revised September 27, 2001
PRELIMINARY
Pin Definitions
Pin Name CPU0:3 Pin No. 40, 39, 36, 35 8, 10, 11, 13, 14, 16, 17 7 Pin Type O Pin Description
W204
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:3 start beginning with a full clock cycle (2-3 CPU clock latency). PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. SPREAD# Input: When brought low this pin activates Spread Spectrum clocking. I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. 24-MHz or 48-MHz Output/Frequency Select 1: 24 MHz output when pin 1 is strapped through 10-K resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-K resistor to GND. This pin also serves as the select strap to determine device operating frequency as described in Table 1. I/O Dual-Function REF0 and SEL48# pin: During power-on, SEL48# input will be latched which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0 fixed output. Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection 0: Selects power-up default CPU clock frequency as shown in Table 1. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are actively held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (23 CPU clock cycle latency). When brought high, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Power Connection: Connect to 3.3V supply. Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect to 2.5V. Ground Connections: Connect all ground pins to the common system ground plane.
PCI1:7
O
PCI_F
O
CPU_STOP#
30
I
PCI_STOP#
31
I
SPREAD# APIC0:1 48MHz 24_48MHz/FS1
28 45, 44 22 23
I O O O
REF0/SEL48#
1
I/O
REF1:2 FS0 SCLK SDATA X1
2, 47 25 26 27 4
O I I I/O I
X2 PWR_DWN#
5 29
I I
VDDQ3 VDDQ2 GND
9, 15, 19, 21, 33, 48 46, 41, 37 3, 6, 12, 18, 20, 24, 32, 34, 38, 43
P P G
Document #: 38-07264 Rev. **
Page 2 of 16
PRELIMINARY
Overview
The W204, a motherboard clock synthesizer, can provide either a 2.5V or 3.3V CPU clock swing making it suitable for a variety of CPU options. A fixed 48-MHz clock is provided for other system functions. The device W204 supports spread spectrum clocking for reduced EMI.
W204
three-stated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is then latched. Next the output buffer is enabled which converts the l/O pin into an operating clock output. The 2-ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is 40 (nominal) which is minimally affected by the 10-K strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the associated output frequencies are delivered on the pins, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor Clock Load
Functional Description
I/O Pin Operation Pins 1 and 23 are dual-purpose l/O pins. Upon power-up these pins act as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-K "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0", connection to VDD sets a latch to "1". Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon W204 power-up, the first 2 ms of operation is used for input logic selection. During this period, pins 1 and 23 are
10 k (Load Option 1) W204 Power-on Reset Timer Output Buffer Output Three-state
Q
Hold Output Low
D
10 k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options Output Strapping Resistor Series Termination Resistor 10 k W204 Power-on Reset Timer Output Buffer Output Three-state
Q
VDD
R Resistor Value R
Clock Load
Hold Output Low
D
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07264 Rev. **
Page 3 of 16
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