|
Details, datasheet, quote on part number:W209C
| |
| Part: | W209C |
| Category: | Timing Circuits => Real Time Clocks |
| Description: | Frequency Generator For Integrated Core Logic With 133-mhz FSB |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W209C datasheet File size : 169 kB |
| Request For quote: | Find where to buy W209C
|
| |
Datasheet text preview:
PRELIMINARY
W209C
Frequency Generator for Integrated Core Logic with 133-MHz FSB
Features
· Maximized EMI suppression using Cypress's Spread Spectrum technology · Low jitter and tightly controlled clock skew · Highly integrated device providing clocks required for CPU, core logic, and SDRAM · Two copies of CPU clock · Nine copies of SDRAM clock · Eight copies of PCI clock · One copy of synchronous APIC clock · Two copies of 66-MHz outputs · Two copies of 48-MHz outputs · One copy of selectable 24- or 48-MHz clock · One copy of double strength 14.31818-MHz reference clock · Power-down control · SMBus interface for turning off unused clocks Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 75.3 95.0 129.0 150.0 150.0 110.0 140.0 144.0 68.3 105.0 138.0 140.0 66.8 100.2 133.6 133.6 157.3 160.0 146.6 122.0 127.0 122.0 117.0 114.0 80.0 78.0 166.0 160.0 66.6 100.0 133.3 133.3 SDRAM 3V66 1 13.0 75. 3 95.0 1 29.0 1 13.0 1 50.0 1 10.0 1 40.0 1 08.0 1 02.5 1 05.0 1 38.0 1 05.0 1 00.2 1 00.2 1 33.6 1 00.2 1 18.0 1 20.0 1 10.0 91.5 1 27.0 1 22.0 1 17.0 1 14.0 1 20.0 1 17.0 1 66.0 1 60.0 1 00.0 1 00.0 1 33.3 1 00.0 63. 3 86. 0 PCI 37.6 31.6 43.0 APIC 18.8 15.8 21.5 18.8 25.0 18.3 23.3 18.0 17.0 17.5 23.0 17.5 16.7 16.7 22.2 16.7 19.6 20.0 18.3 15.2 21.1 20.3 19.5 19.0 20.0 19.5 13.8 13.3 16.6 16.6 22.2 16.6 SS O FF 0. 6% O FF O FF O FF O FF O FF O FF O FF O FF O FF O FF ±0.45% ±0.45% ±0.45% ±0.45% O FF O FF O FF 0. 6% O FF 0. 6% O FF O FF O FF O FF O FF O FF 0. 6% 0. 6% 0. 6% 0. 6%
75. 3 37.6 100 .0 50.0 73. 0 93. 3 72. 0 68. 3 70. 0 92. 0 70. 0 66. 8 66. 8 89. 1 66. 8 78. 6 80. 0 73. 3 61. 0 84. 6 81. 3 78. 0 76. 0 80. 0 78. 0 55. 3 53. 3 66. 6 66. 6 88. 9 66. 6 36.6 46.7 36.0 34.1 35.0 46.0 35.0 33.4 33.4 44.4 33.4 39.3 40.0 36.6 30.5 42.3 40.6 39.0 38.0 40.0 39.0 27.6 26.7 33.3 33.3 44.4 33.3
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .... 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:......... 500 ps CPU, 3V66 Output Skew:........... 175 ps SDRAM, APIC, 48-MHz Output Skew:...... 250 ps PCI Output Skew: ....... 500 ps CPU to SDRAM Skew (@ 133 MHz) ..... ± 0.5 ns CPU to SDRAM Skew (@ 100 MHz) ........ 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz)...... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead) .. 1.5 to 3.5 ns PCI to APIC Skew ..... ± 0.5 ns
Block Diagram
X1 X2 XTAL OSC
PLL REF FREQ
VDDQ3 REF2X/FS3*
Pin Configuration [1]
REF2x /F S3* V DDQ 3 X1 X2 G ND V DDQ 3 3V66_0 3V66_1 G ND F S0*/P CI0 F S1*/P CI1 F S2*/P CI2 G ND P C I3 P C I4 V DDQ 3 P C I5 P C I6 P C I7 G ND 4 8 M H z_ 0 F S4*/48M Hz_1 S I0/24_48#M Hz* V DDQ 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V D D Q2 A PIC V D D Q2 CP U0 CP U1 G ND V D D Q3 S DRAM 0 S DRAM 1 S DRAM 2 G ND S DRAM 3 S DRAM 4 S DRAM 5 V D D Q3 S DRAM 6 S DRAM 7 DCLK G ND P WRDWN#^ S CLK V D D Q3 G ND S DATA
VDDQ2 Divider, Delay, and Phase Control Logic CPU0:1
2
SDATA SCLK
SMBus Logic
APIC VDDQ3
2
(FS0:4*)
W209C
3V66_0:1 FS0*/PCI0 FS1*/PCI1 FS2*/PCI2
PLL 1
5
PCI3:7 SDRAM0:7
PWRDWN#
8
DCLK VDDQ3 48MHz_0
PLL2
/2
FS4*/48MHz_1 SI0/24_48#MHz*
Note: 1. Int erna l pull-down or pull-up resistors present on inputs marked with * or ^ respectively. Design should not rely solely on internal pull-up or pull-down resistor to set I/O pins HIGH or LOW respectively.
Cypress Semiconductor Corporation
·
3901 Nor th First Street
·
San Jose
·
C A 95134 · 408-943-2600 November 16, 2000, Rev. *C
PRELIMINARY
I
W209C
Pin Definitions
Pin Name REF2x/FS3 Pin No. 1 Pi n Type I/O Pin Description Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via SMBus interface. 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 1). 48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output. 48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device. During power up, it also serves as a selection strap. If it is sampled HIGH, the output frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz. Pow er Down Control: LVTTL-compatible input that places the device in powerdown mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 1). Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
X1 X2 FS0*/PCI0
3 4 10
I I I/O
FS1*/PCI1
11
I/O
FS2*/PCI2
12
I/O
PCI3:7 3V66_0:1 4 8 MH z _ 0 FS4* / 4 8 MH z _ 1 SI O/ 24_48#MHz* PWRDWN # CPU0: 1 SDRAM 0:7, DC LK API C SDATA SCLK VDDQ 3 VDDQ 2 G ND
14, 15, 17, 18, 19 7, 8 21 22
O O O I/O
23
I/O
29 45, 44 41, 40, 39, 37, 36, 35, 33, 32, 31 47 25 28 2, 6, 16, 24, 27, 34, 42 46, 48 5, 9, 13, 20, 26, 30, 38, 43,
I O
O O I/O I P P G
2
PRELIMINARY
Output Strapping Resistor Series Termination Resistor W209C Power-on Reset Timer Clock Load Output Buffer Output Three-state
Q
W209C
Hold Output Low
D
10k
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Over view
The W209C is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation Pin # 1, 10, 11, 12, 22, and 23 are dual-purpose l/O pins. Upon power-up the pin acts as a logic input. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency
10 ns 20 ns
is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target, but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W209C when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs.
0 ns
30 ns
40 ns
CPU 100 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz 3V6 6 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC
Hub-PC
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
3
|
|
