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Details, datasheet, quote on part number:W210
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| Part: | W210 |
| Category: | Timing Circuits => Clock Generators => CPU/Memory Specific PLL |
| Description: | Spread Spectrum FTG For Via K7 Chipset |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W210 datasheet File size : 167 kB |
| Request For quote: | Find where to buy W210
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Datasheet text preview:
W 210
Spread Spectrum FTG for VIA K7 Chipset
Features
· Maximized EMI Suppression using Cypress's Spread Spectrum technology · Single-chip system frequency synthesizer for VIA K7 chipset · One pair of differential CPU outputs for K7 Processor · One open-drain CPU output for VIA K7 chipset · Six copies of PCI output · One 48-MHz output for USB · One 24-MHz or 48-MHz output for SIO · Two buffered reference outputs · Thirteen SDRAM outputs provide support for 3 DIMMs · Suppor ts frequencies up to 200 MHz · I2CTM interface for programming · Power management control inputs · Available in 48-pin SSOP Table 1. Mode Input Table M ode 0 1 Pi n 2 CPU_STOP# REF 0
Key Specifications
CPU to CPU Output Skew: ........ 175 ps PCI to PCI Output Skew: ........... 500 ps VDDQ3: ........... 3.3V±5%
Table 2. Pin Selectable Frequency Input Address CPU FS3 FS2 FS1 FS0 (MHz) 1 1 1 1 133.3 1 1 1 0 75 1 1 0 1 100.2 1 1 0 0 66.8 1 0 1 1 79 1 0 1 0 110 1 0 0 1 115 1 0 0 0 120 0 1 1 1 133.3 0 1 1 0 83.3 0 1 0 1 100.2 0 1 0 0 66.8 0 0 1 1 124 0 0 1 0 129 0 0 0 1 138 0 0 0 0 143
PCI0:5 (MHz) 33.3 37.5 33.3 33.4 39.5 36.7 38.3 30 33.3 27.7 33.3 33.4 31.0 32.3 34.5 35.8
Spread Spectrum ±0.5% ±0.5% ±0.5% ±0.5% OF F OF F OF F OF F OF F OF F OF F OF F OF F OF F OF F OF F
Block Diagram
V D DQ 3 R EF0/(C PU_STOP#) X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration
R EF1/F S0
[1]
I/O Pin Control
PWRDWN#
C P U T_ C S Stop Clock Control
÷2,3,4
PLL 1
CP UT 0 CP U C0 V D DQ 3 PC I0/MODE PC I1/FS1 PC I2 PC I3 P CI 4
SDATA SCLK
I2C Logic PLL2
÷2
P CI 5 VDD Q3 48MHz /F S2
VDDQ3 REF0/(CPU_STOP#) GND X1 X2 VDDQ3 PCI0/MODE PCI1/FS1* GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND 2C SDATA I SCLK
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REF1/FS0* GND CPUT_CS GND CPUC0 CPUT0 VDDQ3 PWRDWN#* SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS2* 24_48MHz/FS3^
SDRAMIN
13
24_48MHz /F S3 V DDQ 3 SD RAM0:12
Note: 1. Int erna l pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor.
W 21 0
I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
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3901 Nor th First Street
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San Jose
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C A 95134 · 408-943-2600 April 11, 2000, rev. *C
W210
Pin Definitions
Pin Name CPUT0, CPUC0, CPUT_CS PCI2:5 Pin No. 43, 44, 46 Pin Type O (opendrain) O Pin Description CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs for the K7 processor. CPUT_CS is the open-drain clock output for the chipset. It has the same phase relationship as CPUT0. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine the function of pin 2, see Table 1 for details. PWRDWN# Input: LVTTL-compatible input that places the device in power-down mode when held LOW. In power-down mode,CPUC0 will be three-stated and all the other output clocks will be driven LOW. 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. 24_48-M Hz Output/Frequency Select 3: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Upon power-up, FS0 input will be latched, which will set clock frequencies as described in Table 2. Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0 and CPUT_CS to logic 0, and it will three-state CPUC0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output clock. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when PWRDWN# input is set LOW. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply. Ground Connections: Connect all ground pins to the common system ground plane.
10, 11, 12, 13
PCI1/FS1
8
I/O
PCI0/MODE
7
I/O
PWRDWN#
41
I
48MHz/FS2
26
I/O
24_48MHz/ FS3
25
I/O
REF1/FS0
48
I/O
REF0/ CPU_STOP#
2
I/O
SDRAMIN SDRAM 0:12
15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 24 23 4
I O
SCLK SDATA X1
I I/O I
X2 VDDQ 3
5 1, 6, 14, 19, 27, 30, 36, 42 3, 9, 16, 22, 33, 39, 45, 47
I P
G ND
G
2
W210
Over view
The W210 was developed as a single-chip device to meet the clocking needs of VIA K7 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W210 adds a thir teenth output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. Upon W210 power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled conver ting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is <40 (nominal), which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assum ing that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor 10 k (Load Option 1) W210 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Functional Description
I/O Pin Operation Pins 7, 8, 25, 26, and 48 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
Series Termination Resistor R Clock Load
10 k (Load Option 0)
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W210 Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Resistor Value R
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
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