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Details, datasheet, quote on part number:W224BX
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| Part: | W224BX |
| Category: | Timing Circuits => Clock Generators => Motherboard |
| Description: | Frequency Timing Generators For PC And Server Motherboards |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W224BX datasheet File size : 274 kB |
| Request For quote: | Find where to buy W224BX
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Datasheet text preview:
W224 B 133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
Features
· Maximized EMI suppression using Cypress's Spread Spectrum technology (0.5% and 1.0%) · Single chip system FTG for Mobile IntelŪ Platforms · Three CPU outputs · Seven copies of PCI clock (one Free Running) · Seven SDRAM clock (one DCLK for Memory Hub) · Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video DOT clock · Three 3V66 Hublink/AGP outputs · One VCH clock (48-MHz non-SSC or 66.67-MHz SSC) · Two APIC outputs · One buffered reference output · Supports frequencies up to 133 MHz · Supports 5% and 10% overclocking · SMBus interface for programming · Power management control inputs APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ......... 500 ps CPU Output Skew: ...... 150 ps 3V66 Output Skew: ..... 175 ps APIC, SDRAM Output Skew: ..... 250 ps PCI Output Skew:........500 ps VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: .......... 3.3Vą5% VDDQ2 (CPU, APIC):.... 2.5Vą5% Table 1. Pin Selectable Functions TEST# 0 0 1 1 1 1 FS1 x x 0 0 1 1 FS0 0 1 0 1 0 1 CPU Three-state Test 66 MHz 100 MHz 133 MHz 133 MHz SDRAM Three-state Test 100 MHz 100 MHz 133 MHz 100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:..... 250 ps
Block Diagram
X1 X2
Pin Configuration[1]
VDD_REF REF
XTAL OSC PLL 1
Divider Network
PLL Ref Freq
Stop Clock Control VDD_CPU CPU0 CPU_F1:2
FS0:1 CPU_STP#
VDD_SDRAM SDRAM0:5 DCLK VDD_APIC APIC0:1 PWR_DWN# VDD_PCI PCI_F Stop Clock Control PCI_STP# PCI1:6
VDD_3V66 3V66_0:1 3V66_AGP VDD_48MHz
PLL2
USB (48MHz) DOT (48MHz)
R EF VDD_REF X1 X2 GND_REF GND_3V66 3V66_0 3V66_1 3V66_AGP VDD_3V66 *PCI_STP# PCI_F PCI1 GND_PCI PCI2 PCI3 VDD_PCI PCI4 PCI5 PCI6 GND_PCI VDD_CORE GND_CORE GND_48MHz USB DOT VDD_48MHz F S0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND_APIC APIC0 APIC1 VDD_APIC C PU 0 VDD_CPU C PU _ F 1 C PU _ F 2 GND_CPU GND_SDRAM SDRAM0 SDRAM1 VDD_SDRAM SDRAM2 SDRAM3 GND_SDRAM SDRAM4 SDRAM5 DCLK VDD_SDRAM VCH_CLK VDD_VCH C PU _ ST P# * T EST #* PWR_DWN#* SCLK SDATA F S1
W224B
SDATA SCLK
SMBus Logic
VCH_CLK
Note: 1. Internal pull-up resistors present on inputs marked with [*]. Design should not rely solely on internal pull-up to set I/O pins HIGH.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation Document #: 38-07191 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised December 22, 2002
W224B
Pin Definitions
Pin Name CPU0, CPU_F1:2 PCI1:6, PCI_F APIC0:1 SDRAM0:5, DCLK 3V66_0:1, 3V66_AGP USB DOT REF VCH_CLK PWR_DWN# CPU_STP# PCI_STP# TEST# FS0:1 SCLK SDATA X1 Pin No. 52, 50, 49 13, 15, 16, 18, 19, 20, 12 55, 54 46, 45, 43, 42, 40, 39, 38 7, 8, 9 25 26 1 36 32 34 11 33 28, 29 31 30 3 Pin Type O O O O O O O O O I I I I I I I/O I Pin Description CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial input interface. The CPU0 output is gated by the CLK_STOP# input. 33-MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by the PCI_STOP# input. APIC Output: 2.5V fixed 33.33-MHz clock. This output is synchronous to the CPU clock. SDRAM Output Clocks: 3.3V outputs running at either 100MHz or 133MHz depending on the setting of FS0:1 inputs. DCLK is a free-running clock. 66MHz Clock Outputs: 3.3V fixed 66-MHz clock. USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output. Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal. Reference Clock: 3.3V 14.318-MHz clock output. Video Control Hub Clock Output: 3.3V selectable 48MHz non-spread spectrum or 66.67 MHz spread spectrum clock output. Power Down Control: 3.3V LVTTL-compatible input that places the device in power down mode when held low. CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0 clock. Output remains in the low state. PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks. Output remains in the low state. Test Mode Control: 3.3V LVTTL-compatible input to place the device into test mode. Frequency Selection Input: 3.3V LVTTL-compatible input used to select the CPU and SDRAM frequencies. See Frequency Table. SMBus Clock Input: Clock pin for SMBus circuitry. SMBus Data Input: Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
X2 VDD_REF, VDD_3V66, VDD _PCI, VDD_48MHz, VDD_VCH, VDD_SDRAM, VDD_SDRAM VDD_APIC, VDD_CPU
4 2, 10, 17, 27, 35, 37, 44
O P
51, 53
P
2.5V Power Connection: Power supply for APIC and CPU output buffers. Connect to 2.5V.
Document #: 38-07191 Rev. *A
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W224B
Pin Definitions
Pin Name GND_REF, GND_3V66, GND_PCI, GND_PCI, GND_48MHz, GND_SDRAM, GND_SDRAM, GND_CPU, GND_APIC VDD_CORE GND_CORE Pin No. 5, 6, 14, 21, 24, 41, 47, 48, 56 Pin Type G Pin Description Ground Connection: Connect all ground pins to the common system ground plane.
22 23
P G
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. Analog Ground Connection: Ground for core logic, PLL circuitry.
Overview
The W224 is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel architecture platform using graphics integrated core logic.
CPU/SDRAM Frequency Selection
CPU output frequency is selected through pins 28 and 29. For CPU/SDRAM frequency programming information, refer to Table 2. Alternatively, frequency selections are available through the serial data interface.
Table 2. Frequency Select Truth Table
TEST# FS1 FS 0 CPU S DRAM 3V 66 PCI 48MHz RE F APIC
Notes 2 3, 4 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7
0 0 1 1 1 1
X X 0 0 1 1
0 1 0 1 0 1
Hi-Z TCLK/2 66 MHz 100 MHz 133 MHz 133 MHz
Hi-Z TCLK/2 100 MHz 100 MHz 133 MHz 100 MHz
Hi-Z TCLK/3 66 MHz 66 MHz 66 MHz 66 MHz
Hi-Z TCLK/6 33 MHz 33 MHz 33 MHz 33 MHz
Hi-Z TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz
Hi-Z TCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
Hi-Z TCLK/6 33 MHz 33 MHz 33 MHz 33 MHz
Notes: 2. Provided for board-level "bed of nails" testing. 3. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 4. Required for DC output impedance verification. 5. "Normal" mode of operation. 6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07191 Rev. *A
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