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Details, datasheet, quote on part number:W228BH
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| Part: | W228BH |
| Category: | Timing Circuits => Clock Generators => Motherboard |
| Description: | Frequency Timing Generators For PC And Server Motherboards |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W228BH datasheet File size : 177 kB |
| Request For quote: | Find where to buy W228BH
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Datasheet text preview:
W228 B
FTG for Integrated Core Logic with 133-MHz FSB
Features
· Maximized EMI suppression using Cypress's Spread Spectrum technology · Two copies of CPU clock at 66/100/133 MHz · Thirteen copies of 100-MHz SDRAM clocks · Two copies of PCI clock · One copy of APIC clock at 33 MHz, synchronous to CPU clock · Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock · Three copies of 3V 66-MHz fixed clock · One copy of 14.31818-MHz reference clock · Power down control · SMBus interface for turning off unused clocks CPU, 3V66 Output Skew:...........175 ps PCI Output Skew:........500 ps CPU to SDRAM Skew (@ 133 MHz):.......±0.5 ns CPU to SDRAM Skew (@ 100 MHz):........4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): ..... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):..1.5 to 3.5 ns PCI to APIC Skew: ..... ±0.5 ns Table 1. Pin Selectable Functions Tristate# 0 0 1 1 1 1 FSEL0 0 1 0 1 0 1 FSEL1 x x 0 0 1 1 CPU Three-state Test 66 MHz 100 MHz 133 MHz 133 MHz SDRAM Three-state Test 100 MHz 100 MHz 133 MHz 100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:..... 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:......... 500 ps APIC, SDRAM Output Skew: ..... 250 ps
Block Diagram
VDDQ3
Pin Configuration [1]
APIC VDDQ2 GND REF0/FSEL1* VDDQ3 X1 X2 GND VDDQ3 3V66_0 3V66_1 3V66_AGP GND VDDQ3 PCI0_ICH PCI1 GND FSEL0 GNDA VDDA PWRDWN# SCLK SDATA GND VDDQ3 USB DOT Tristate# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 GND CPU0 CPU1 GND SDRAM0 SDRAM1 VDDQ3 GND SDRAM2 SDRAM3 SDRAM4 VDDQ3 GND SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 VDDQ3 GND SDRAM10 SDRAM11 VDDQ3 GND SDRAM12
X1 X2
XTAL OSC
PLL REF FREQ
REF0/FSEL1
VDDQ2
SDATA SCLK
SMBus Logic
Divider, Delay, and Phase Control Logic
2
CPU0:1
W228B
APIC VDDQ3
FSEL1:0 VDDA
PLL 1
2
3V66_0:1 3V66_AGP PCI0_ICH
Tristate#
PCI1 SDRAM0:12
13
PWRDWN# VDDQ3 USB DOT
VDDA
PLL2
Note: 1. Internal pull-down resistors present on input marked with *. Design should not solely rely on internal pull-down resister to set I/O pin LOW.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation Document #: 38-07180 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised December 22, 2002
W228B
Pin Definitions
Pin Name REF0/FSEL1 X1 X2 PCI0_ICH, PCI1 3V66_0:2, 3V66_AGP USB DOT Tristate#, FSEL0 PWRDWN# CPU0 :1 Pin No. 4 6 7 15, 16 10, 11, 12 26 27 28, 18 21 54, 53 Pin Type I/O I O O O O O I I O Pin Description Reference Clock: 3.3V 14.318-MHz clock output. This pin also serves as a strap option for CPU frequency selection. See Table 1 for detailed descriptions. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output: A connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI Clock 0 through 1: 3.3V 33-MHz PCI clock outputs. PCI1 can be individually turned off via SMBus interface. 66-MHz Clock Output: 3.3V fixed 66-MHz clock. USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output. Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal. Clock Function Selection pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions. Power-Down Control: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface and integrated test port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the configuration of SEL0:1 and SEL133. Voltage swing set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:12 can be individually turned off via SMBus interface.
SDRAM0:12
51, 50, 47, 46, 45, 42, 41, 38, 37, 36, 33, 32, 29 1 23 22 5, 9, 14, 25, 31, 35, 40, 44, 49 20 2, 56 3, 8, 13, 17, 24, 30, 34, 39, 43, 48, 52, 55 19
O
APIC SDATA SCLK VDDQ3
O I/O I P
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs (33 MHz). Voltage swing set by VDDQ2. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. Ground Connections: Connect all ground pins to the common system ground plane.
VDDA VDDQ2 GND
P P G
GNDA
G
Document #: 38-07180 Rev. *A
Page 2 of 16
W228B
VDD Output Strapping Resistor 10 k (Load Option 1) W228B Power-on Reset Timer Output Buffer Output Three-state
Q
Series Termination Resistor Clock Load
Hold Output Low
D
10k (Load Option 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W228B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Pin Selectable Functions Table 2 outlines the device functions selectable through Tristate# and FSEL0:1. Specific outputs available at each pin are detailed in Table 2 below.
Functional Description
I/O Pin Operation REF0/FSEL1 is a dual-purpose l/O pin. Upon power-up the pin acts as a logic input for FSEL1 selection (see Table 1 and Table 2). If the pin is strapped to a HIGH state externally, CPU will be strapped LOW. CPU clock outputs will be determined by the status of SEL0:1 input pins. An external 10-k strapping
Table 2. CK Whitney Truth Table Tristate# 0 0 1 1 1 1 FSEL0 0 1 0 1 0 1 FSEL1 X X 0 0 1 1 CPU Hi-Z TCLK/4 66 MHz 100 MHz 133 MHz 133 MHz SDRAM Hi-Z TCLK/4 100 MHz 100 MHz 133 MHz 100 MHz 3V66 Hi-Z TCLK/6 66 MHz 66 MHz 66 MHz 66 MHz PCI Hi-Z TCLK/12 33 MHz 33 MHz 33 MHz 33 MHz 48MHz Hi-Z TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz REF Hi-Z TCLK 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz APIC Hi-Z TCLK/12 33 MHz 33 MHz 33 MHz 33 MHz Notes 2 4, 5 3, 6, 7 3, 6, 7 3, 6, 7 3, 6, 7
Notes: 2. Provided for board-level "bed of nails" testing. 3. "Normal" mode of operation. 4. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 5. Required for DC output impedance verification. 6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07180 Rev. *A
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