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Details, datasheet, quote on part number:W245-30H
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W245-30
Frequency Multiplying, Peak Reducing EMI Solution
Features
· Cypress PREMISTM family offering · Generates an EMI optimized clocking signal at the output · Selectable output frequency range · Single 1.25%, 2.5%, 5% or 10% down or center spread output · Integrated loop filter components · Operates with a 3.3 or 5V supply · Low power CMOS design · Available in 20-pin SSOP (Small Shrunk Outline Package)
Key Specifications
Supply Voltages:........ VDD = 3.3Vą0.3V or VDD = 5Vą10% Frequency range: ... 13 MHz < Fin < 120 MHz Cycle to Cycle Jitter: ........250 ps (max) Output duty cycle: .........40/60% (worst case)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration [1, 2]
SSOP
X1 XTAL Input X2
W245-30
SDATA SCLK IIC Interface
Spread Spectrum Output (EMI suppressed)
X1 X2 AVDD MW 0^ SDATA O R 1^ S CLK GND O R 2* SSON#^
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
REFOUT V DD GND I R 1* I R 2* SSOUT M W 1* G ND V DD M W 2^
W245-30
3.3V or 5.0V
Oscillator or Reference Input
X1
W245-30
SDATA IIC Interface SCLK
Spread Spectrum Output (EMI suppressed)
Notes: 1. Pins marked with ^ are internal pull-down resistors with weak 250 k. 2. Pins marked with * are internal pull-up resistors with weak 80 k.
Cypress Semiconductor Corporation Document #: 38-07229 Rev. *B
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised August 13, 2002
W245-30
Pin Description
Pin Name SSOUT REFOUT Pin No. 15 20 Pin Type O O Pin Description Output Modulated Frequency: Frequency modulated copy of the input clock (SSON# asserted). Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection: When Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal. MW1:Down, MW1:Up, MW2:Down (See Table 2). Reference Frequency Selection: Logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. Output Frequency Selection Bits: These pins select the frequency operation for the output. Refer to Table 1. OR2 pin have internal pull-up resistors. OR1 pin have internal pull-down resistors. Clock pin for SMBus circuitry. Data pin for SMBus Circuitry. Power Connection: Connected to 3.3V or 5V power supply. Analog Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common ground plane.
X1
1
I
X2 SSON#
2 10
I I
MW0:2
4, 11, 14
I
IR1:2
17, 16
I
OR1:2
6, 9
I
SCLK SData VDD AVDD GND
7 5 12, 19 3 8, 13, 18
I I/O P P G
Document #: 38-07229 Rev. *B
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W245-30
Table 1. Frequency Configuration (Frequencies in MHz) Range of Fin Frequency Min. 14 14 14 25 25 25 50 50 50 Reserved Power Down Hi-Z Power Down 0 Power Down 1 Max. 30 30 30 60 60 60 120 120 120 Multiplier Settings OR2 0 1 1 0 1 1 0 1 1 0 0 0 0 OR1 1 0 1 1 0 1 1 0 1 0 0 0 0 1 2 4 0.5 1 2 0.25 0.5 1 N/A N/A N/A N/A Output / Input Range of Fout Min. 14 28 56 13 25 50 13 25 50 N/A N/A N/A N/A Max. 30 60 120 30 60 120 30 60 120 N/A N/A N/A N/A Required R Settings IR2 0 0 0 1 1 1 1 1 1 As Set As Set As Set As Set IR1 1 1 1 0 0 0 1 1 1 As Set As Set As Set As Set 1 1 0 0 Modulation & Power Down Settings MW2 MW1 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 0 1 0 1
Table 2. Modulation Width Selection Table EMI Reduction Modulation Setting MW2 Minimum EMI Control Suggested Setting Alternate Setting Maximum EMI reduction 0 0 1 1 MW1 0 1 0 1 Bandwith Limit Frequencies as a% Value of Fout MW0 = 0 Low 98.75% 97.5% 95.0% 90.0% High 100% 100% 100% 100% Low 99.375% 98.75 97.5% 95% MW0 = 1 High 100.625 101.25% 102.5% 105%
Overview
The W245-30 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation.
times the reference frequency. (Note: For the W245-30 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pins MW0:2 as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided.
Functional Description
The W245-30 uses a phase locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q Document #: 38-07229 Rev. *B
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