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Details, datasheet, quote on part number:W250-03
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Datasheet text preview:
3
PRELIMINARY
W250-03
FTG for VIA Apollo Pro-266
Features
· Maximized EMI Suppression using Cypress's Spread Spectrum Technology · System frequency synthesizer for VIA Apollo Pro-266 · Supports Intel® Pentium® II and Pentium® III class proce sso r · Three copies of CPU output · Nine copies of PCI output · One 48-MHz output for USB · One 24-MHz or 48-MHz output for SIO · Two buffered reference outputs · Three copies of APIC output · Supports frequencies up to 200 MHz · SMBus interface for programming · Power management control inputs · Available in 48-pin SSOP Key Specifications CPU Cycle-to-Cycle Jitter: ...... 250 ps CPU to CPU Output Skew: ..... 175 ps PCI Cycle to Cycle Jitter: ........ 500 ps PCI to PCI Output Skew: ........ 500 ps
Table 1. Pin Selectable Frequency (continued)
Input Address FS4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 PCI (MHz) 33.3 31.7 30.0 28.3 41.5 Spread Spectrum OFF OFF OFF OFF OFF 1 1 1 1 1 1 1 FS3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU, (MHz) 160.0 150.0 145.0 140.0 136.0 130.0 124.0 66.6 100.0 118.0 133.3 66.8 100.2 115.0 133.6 66.8 100.2 110.0 133.6 105.0 90.0 85.0 78.0 66.6 100.0 75.0 133.3 AGP 80.0 75.0 72.5 70.0 68.0 65.0 62.0 66.6 66.6 78.7 66.6 66.8 66.8 76.7 66.8 66.8 66.8 73.3 66.8 70.0 60.0 56.7 78.0 66.6 66.6 75.0 66.6 PCI (MHz) 40.0 37.5 36.3 35.0 34.0 32.5 31.0 33.3 33.3 39.3 33.3 33.4 33.4 38.3 33.4 33.4 33.4 36.7 33.4 35.0 30.0 28.3 39.0 33.3 33.3 37.5 33.3 Spread Spectrum OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF +0.25% +0.25% OFF +0.25% +0.5% +0.5% OFF +0.5% OFF OFF OFF OFF -0.5% -0.5% OFF -0.5%
Table 1. Pin Selectable Frequency
Input Address FS4 0 0 0 0 0 FS3 0 0 0 0 0 FS2 0 0 0 0 1 FS1 0 0 1 1 0 FS0 0 1 0 1 0 CPU, (MHz) 200.0 190.0 180.0 170.0 166.0 AGP 66.6 63.3 60.0 56.7 83.0
Block Diagram
VDD_REF REF0 X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration[1]
VD D_ REF GN D_ REF X1 X2 VDD_48 MHz FS3*/48 MHz FS2*/24_48 MHz GND_48 MHz PCI_F PCI 1 PCI 2 GND_PCI PCI 3 PCI 4 VDD_PCI PCI 5 PCI 6 PCI 7 GND_PCI PCI 8 *FS1 *FS0 AG P0 VDD_AGP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF 0 REF 1 /F S4 * VDD_APIC APIC0 APIC1 GND_APIC APIC2 VDD_CPU GN D_ CP U CPU 1 CPU 2 VDD_CPU GN D_ CP U CPU 3 CPU_STOP#* PCI_STOP#* PWR_DWN#* VDD_CORE GN D_ CO RE SDATA SCL K AG P2 AG P1 GN D_ A G P
REF1/FS4 VDD_APIC APIC0:2 VDD_AGP AGP0:2 VDD_CPU
DIV DIV CPU_STOP# PWR_DWN# FS0:1
W250-03
PLL 1
÷2,3,4
Stop Clock Control
CPU1:3 VDD_PCI PCI_F
PCI_STOP#
Stop Clock Control SMBus Logic PLL2
÷2
PCI1:8
SDATA SCLK
VDD_48 MHz 48MHz/FS3
Note: 1. Signals marked with `*' have internal pull-up resistors.
24_48MHz/FS2
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation Document #: 38-07254 Rev. **
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised September 27, 2001
PRELIMINARY
Pin Definitions
Pin Name CPU1:3 CPU_STOP#* PCI1:8 Pin No. 39, 38, 35 34 10, 11, 13, 14, 16, 17, 18, 20 33 9 32 45, 44, 42 6 Pin Type O I O Pin Description
W250-03
CPU Clock Output: Frequency is set by the FS0:4 input or through serial input interface. The CPU1:3 output are gated by the CLK_STOP# input. CPU Output Control: 3.3V LVTTL compatible input that stop CPU1:3 clocks. PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through serial input interface, see Table 1 and Table 5 for details. Output voltage swing is controlled by voltage applied to VDD_PCI. PCI_STOP# Input: 3.3V LVTTL compatible input that stops PCI1:8. Free-Running PCI Clock Output: Output voltage swing is controlled by the voltage applied to VDD_PCI. See Table 1. and Table 5. for detailed frequency information. PWR_DWN# Input: LVTTL-compatible input that places the device in power-down mode when held LOW. APIC Clock Output: APIC clock outputs. The output voltage swing is controlled by VDD_APIC. 48-MHz Output/Frequency Select 3: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 1. 24_48-MHz Output/Frequency Select 2: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 1. Reference Clock Output 1/Frequency Select 4: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 1. Upon power-up, FS4 input will be latched which will set clock frequencies as described in Table 1. Reference Clock Output 0: 3.3V 14.318 MHz output clock. Clock pin for serial interface circuitry. Data pin for serial interface circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. FS0, FS1 Inputs: Latched frequency select inputs. These latched input serve as a poweron strap option to determine device operating frequency as described in Table 1. AGP Outputs: Output frequency is set by FS0:4 inputs or through serial interface. Power Connection: Power supply for core logic, PLL circuitry, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply.
PCI_STOP#* PCI_F PWR_DWN#* APIC0:2 48MHz/FS3*
O O I O I/O
24_48MHz/ FS2*
7
I/O
REF1/FS4*
47
I/O
REF0 SCLK SDATA X1
48 28 29 3
O I I/O I
X2 FS0,FS1 AGP0:2 VDD_REF, VDD_48MHz, VDD_PCI, VDD_AGP, VDD_CORE VDD_CPU, VDD_APIC
4 22, 21 23, 26, 27 1, 5,15, 24, 31
I I O P
41, 46, 37
P
Power Connection: Power supply for APIC and CPU1 output buffers, connect to 2.5V.
Document #: 38-07254 Rev. **
Page 2 of 13
PRELIMINARY
Pin Definitions (continued)
Pin Name GND_REF, GND_48MHz, GND_PCI, GND_AGP, GND_CORE, GND_CPU, GND_APIC Pin No. 2, 8, 12, 19, 25, 30, 36, 40, 43 Pin Type G Pin Description
W250-03
Ground Connections: Connect all ground pins to the common system ground plane.
Document #: 38-07254 Rev. **
Page 3 of 13
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