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Details, datasheet, quote on part number:W312-02
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| Part: | W312-02 |
| Category: | Timing Circuits => Clock Generators |
| Description: | FTG For Via KT266 Chipset With Programmable Output Frequency |
| Company: | Cypress Semiconductor Corp. |
| Datasheet: | Download W312-02 datasheet File size : 157 kB |
| Request For quote: | Find where to buy W312-02
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Datasheet text preview:
PRELIMINARY
W312-02
FTG for VIA KT266 Chipset with Programmable Output Frequency
Features
· Single chip FTG solution for VIA KT266 Chipset · Programmable clock output frequency with less than 1 MHz increment · Integrated fail-safe Watchdog timer for system recovery · Automatically switch to HW selected or SW programmed clock frequency when watchdog timer time-out · Capable of generate system RESET after a watchdog timer time-out occurs or a change in output frequency via SMBus interface · Support SMBus byte read/write and block read/ write operations to simplify system BIOS development · Vendor ID and Revision ID support · Programmable drive strength for PCI output clocks · Programmable output skew between CPU, AGP and PCI · Maximized EMI suppression using Cypress's Spread Spectrum Technology · · · · · · · · Low jitter and tightly controlled clock skew Two pairs of differential CPU clocks Eleven copies of PCI clocks Three copies of 66-MHz outputs Two copies of 48-MHz outputs Three copies of 14.31818-MHz reference clocks One RESET output for system recovery Power management control support
Key Specifications
CPU Outputs Cycle-to-Cycle Jitter: ....250 ps 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ......... 500 ps CPU, 3V66 Output Skew:...........200 ps 48-MHz Output Skew: ....... 250 ps PCI Output Skew:........500 ps
Block Diagram
VDD_REF
REF2 REF1/FS1* REF0/FS0*
Pin Configuration [1]
VDD_REF GND_REF X1 X2 VDD_48MHz *FS2/48MHz *FS3/24_48MHz GND_48MHz *FS4/PCI_F *SEL24_48#/PCI0 PCI1 GND_PCI PCI2 PCI3 VDD_PCI PCI4 PCI5 PCI6 GND_PCI PCI7 PCI8 PCI9_E VDD_PCI RST# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/FS0* REF1/FS1* REF2 REF_STOP#* AGP_STOP#* GND_CPU CPUT0 CPUC0 VDD_CPU CPUT_CS CPUC_CS GND_CPU CPU_STOP#* PCI_STOP#* PD#* VDD_CORE GND_CORE SDATA SCLK GND_AGP AGP2 AGP1 AGP0 VDD_AGP
X1 X2
XTAL OSC
PLL REF FREQ
Divider, Delay, and Phase Control Logic
VDD_CPU CPUT0,CPUC0
2
SDATA SCLK
SMBus Logic
CPUT_CS,CPUC_CS VDD_AGP
3
W312-02
AGP0:2
(FS0:4) VDD_PCI PCI0/SEL24_48#*
PLL 1
PD# CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP#
5
PCI1:8 PCI9_E
RST# VDD_48MHz 48MHz/FS3*
PLL2
/2
SEL24_48#*
24_48MHz/FS4*
Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation Document #: 38-07259 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised September 27, 2001
PRELIMINARY
I
W312-02
Pin Definitions
Pin Name REF0/FS0 Pin No. 48 Pin Type I/O Pin Description Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock output. REF0 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 4. Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock output. REF1 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 4. Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be disabled when REF_STOP# is active. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 4. PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output will be disabled when PCI_STOP# is active. This pin also serves as the select strap to determine device operating frequency of 24_48MHz output. PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled when PCI_STOP# is active. Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled when PCI_STOP# is active. AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency is controlled by FS0:4 (see Table 4). AGP0:2 will be disabled when AGP_STOP# is active. 48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum output. 48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 4. 24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 4.
REF1/FS1
47
I/O
REF2 X1 X2 PCI_F/FS4
46 3 4 9
I/O I I I
PCI_0/SEL24_48#
10
I/O
PCI1:8 PCI9_E AGP0:2
11, 13, 14, 16, 17, 18, 20, 21 22 26, 27, 28
O O O
48MHz/FS2
6
I/O
24_48MHz/FS3
7
I/O
RST#
24
Reset#: Open-drain RESET# output. O (opendrain) O CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock out(open- puts for the K7 processor. They are open-drain outputs. drain) O CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential CPU clock outputs for the chipset. They are push-pull outputs. These outputs will be disabled when CPU_STOP# is active. CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is active. PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active. AGP STOP Input: This input will disable AGP0:2 when it is active. REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active.
CPUT0, CPUC0
42, 41
CPUT_CS, CPUC_CS CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP#
39, 38
36 35 44 45
I I I I
Document #: 38-07259 Rev. **
Page 2 of 21
PRELIMINARY
Pin Definitions (continued)
Pin Name PD# SDATA SCLK VDD_CPU VDDQ_AGP VDDQ_PCI VDDQ_48MHz VDD_REF VDD_Core GND_REF, GND_48MHz, GND_PCI, GND_AGP, GND_Core, GND_CPU Pin No. 34 31 30 40 25 15, 23 5 1 33 2, 8, 29, 32, 37, 43 Pin Type I I/O I P P P P P P G Pin Description
W312-02
Power-Down Input: This input will trigger the clock generator into Power Down mode when it is active. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 2.5V Power Connection: Power supply for CPU output buffers. Connect to 2.5V. 3.3V Power Connection: Power supply for AGP output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for reference output buffers. Connect to 3.3V. 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
Document #: 38-07259 Rev. **
Page 3 of 21
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