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Details, datasheet, quote on part number:W320-04
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Datasheet text preview:
PRELIMINARY
W320-04
200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs
2W 320 -04
Features · Compliant to IntelŪ CK-Titan Clock Synthesizer/Driver Specifications · Multiple output clocks at different frequencies -- Three pairs of differential CPU outputs, up to 200 MHz -- Ten synchronous PCI clocks, three free-running -- Six 3V66 clocks -- Two 48-MHz clocks -- One reference clock at 14.318 MHz -- One VCH clock · Spread Spectrum clocking (down spread) · Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) · OE and Test Mode support · 56-pin SSOP package and 56-pin TSSOP package
Benefits Supports next generation PentiumŪ processors using differential clock drivers Motherboard clock generator -- Support Multiple CPUs and a chipset -- Support for PCI slots and chipset -- Supports AGP, DRCG reference and Hub Link -- Supports USB host controller and graphic controller -- Supports ISA slots and I/O chip
Enables reduction of EMI and overall system cost Enables ACPI compliant designs
· Three Select inputs (Mode select & IC Frequency Select) Supports up to four CPU clock frequencies Enables ATE and "bed of nails" testing Widely available, standard package enables lower cost
Logic Block Diagram
VDD_REF
PWR
Pin Configurations
SSOP & TSSOP Top View
VDD_REF XTAL_IN XTAL_OUT GND_REF PCI_F0
Stop Clock Control
X1 X2
XTAL OSC
1 2 3 4 5 6 7 8 9 10 11
56 55 54 53 52 51 50 49 48 47 46
REF S1 S0 CPU_STOP# CPU0 CPU#0 VDD_CPU CPU1 CPU#1 GND_CPU VDD_CPU CPU2 CPU#2 MULT0 IREF GND_IREF S2 USB DOT VDD_ 48 MHz GND_ 48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA
REF
PLL Ref Freq PLL 1
S0:2 PWR_GD# CPU_STOP# Divider Network
PWR
Gate
VDD_CPU CPU0:2 CPU#0:2
PCI_F1 PCI_F2 VDD_PCI GND_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI
PWR Stop Clock Control
VDD_PCI PCI_F0:2 PCI0:6
W320-04
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI_STOP#
/2
PWR_DWN#
PWR
VDD_3V66 3V66_0 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN
GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PWR_DWN# VDD_CORE GND_CORE PWR_GD#
PWR
PLL 2
VDD_48MHz
PWR
USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1
SDATA SCLK
SMBus Logic
Intel and Pentium are registered trademarks of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation Document #: 38-07010 Rev. **
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3901 North First Street
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San Jose
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CA 95134 · 408-943-2600 Revised May 21, 2001
PRELIMINARY
Pin Summary
Name REF XTAL_IN XTAL_OUT CPU, CPU# [0:2] 3V66_0 3V66_1/VCH 66IN/3V66_5 66BUFF [2:0] /3V66 [4:2] PCI_F [0:2] PCI [0:6] USB DOT S2 S1, S0 IREF MULT0 PWR_DWN# PCI_STOP# CPU_STOP# PWRGD# Pins 56 2 3 44, 45, 48, 49, 51, 52 33 35 24 21, 22, 23 5, 6, 7, Description 3.3V 14.318-MHz clock output 14.318-MHz crystal input 14.318-MHz crystal input Differential CPU clock outputs 3.3V 66-MHz clock output
W320-04
3.3V selectable through SMBus to be 66 MHz or 48 MHz 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO 33 MHz clocks divided down from 66Input or divided down from 3V66
10, 11, 12, 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from 3V66 39 38 40 54, 55 42 43 25 34 53 28 Fixed 48-MHz clock output Fixed 48-MHz clock output Special 3.3V 3-level input for Mode selection 3.3V LVTTL inputs for CPU frequency selection A precision resistor is attached to this pin which is connected to the internal current reference 3.3V LVTTL input for selecting the current multiplier for the CPU outputs 3.3V LVTTL input for Power_Down# (active LOW) 3.3V LVTTL input for PCI_STOP# (active LOW) 3.3V LVTTL input for CPU_STOP# (active LOW) 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SMBus compatible SDATA SMBus compatible Sclk
SDATA SCLK VDD_REF, VDD_PCI, VDD_3V66, VDD_48 MHz, VDD_CPU VDD_CORE GND_REF, GND_PCI, GND_3V66, GND_IREF, VDD_CPU GND_CORE
29 30
1, 8, 14, 19, 32, 37, 46, 50 3.3V power supply for outputs
26
3.3V power supply for PLL
4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs
27
Ground for PLL
Document #: 38-07010 Rev. **
Page 2 of 18
PRELIMINARY
Function Table[1]
S2 1 1 1 1 0 0 0 0 Mid Mid Mid Mid S1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 S0 CPU (MHz) 66 MHz 100 MHz 200 MHz 133 MHz 66 MHz 100 MHz 200 MHz 133 MHz Hi-Z TCLK/2 Reserved Reserved 3V66[0:1] (MHz) 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved 66BUFF[0:2]/ 3V66[2:4] (MHz) 66IN 66IN 66IN 66IN 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved 66IN/3V66_5 (MHz) 66 MHz Input 66 MHz Input 66 MHz Input 66 MHz Input 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 Reserved Reserved PCI_F/PCI (MHz) 66IN/2 66IN/2 66IN/2 66IN/2 33 MHz 33 MHz 33 MHz 33 MHz Hi-Z TCLK/8 Reserved Reserved REF0(MHz)
W320-04
USB/DOT (MHz)
Notes: 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 1, 5 7, 8, 5 ---
14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz Hi-Z TCLK Reserved Reserved Hi-Z TCLK/2 Reserved Reserved
Swing Select Functions
Mult0 0 1 Board Target Trace/Term Z 60 50 Reference R, IREF = VDD/(3*Rr) Rr = 221 1%, IREF = 5.00 mA Rr = 475 1%, IREF = 2.32 mA Output Current IOH = 4*IREF IOH = 6*IREF VOH @ Z 1.0V @ 50 0.7V @ 50
Clock Driver Impedances
Impedance Buffer Name CPU, CPU# REF PCI, 3V66, 66BUFF USB DOT 3.1353.465 3.1353.465 3.1353.465 3.1353.465 VDD Range Buffer Type Type X1 Type 3 Type 5 Type 3A Type 3B 20 12 12 12 Minimum Typical 50 40 30 30 30 60 55 55 55 Maximum
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP# 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 CPU IREF*2 IREF*2 IREF*2 ON ON CPU# FLOAT FLOAT FLOAT ON ON 3V66 LOW ON ON ON ON 66BUFF LOW ON ON ON ON PCI_F LOW ON ON ON ON PCI LOW OFF ON OFF ON USB/DOT LOW ON ON ON ON VCOS/ OSC OFF ON ON ON ON
Note: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. "Normal" mode of operation 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167PPM to match USB default. 5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. 6. Required for DC output impedance verification. 7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock margining.
Document #: 38-07010 Rev. **
Page 3 of 18
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