|
Details, datasheet, quote on part number:W40S01-04H
| |
Datasheet text preview:
1W 40S0 1-0 4
W40S01-04
SDRAM Buffer - 4 DIMM
Features
· Eighteen skew controlled CMOS outputs (SDRAM0:17) · Supports four SDRAM DIMMs · Ideal for high-performance systems designed around Intel®'s 440BX chip set · SMBus serial configuration interface · Output skew between any two outputs is less than 250 ps · 1 to 5 ns propagation delay · DC to 133-MHz operation · Single 3.3V supply voltage · Low power CMOS design packaged in a 48-pin SSOP (Small Shrink Outline Package)
Key Specifications
Supply Voltages:.... VDDQ3 = 3.3V ± 5% Operating Temperature:... 0 °C to +70°C Input Threshold: ........ 1.5V typical Maximum Input Voltage: .. VDDQ3 + 0.5V Input Frequency:..... 0 to 133 MHz BUF_IN to SDRAM0:17 Propagation Delay: ...... 1.0 to 5.0 ns Output Edge Rate:........ >1.5 V/ns Output Skew: ... ±250 ps Output Duty Cycle: .......... 45/55% worst case Output Impedance:.....15 typical Output Type: ...... CMOS rail-to-rail Par t to Part Skew:........700 ps
Overview
The Cypress W40S01-04 is a low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately 15 which is ideal for driving SDRAM DIMMs.
Block Diagram
SDATA SCLOCK Serial Port Device Control OE SDRAM 0 SDRAM 1 SDRAM 2 SDRAM 3 SDRAM 4 SDRAM 5 SDRAM 6 SDRAM 7 SDRAM 8 BUF_IN SDRAM 9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17
Pin Configuration
SSOP NC NC V DDQ3 SDRAM0 SDRAM1 GND V DDQ3 SDRAM2 SDRAM3 GND BUF_IN V DDQ3 SDRAM4 SDRAM5 GND V DDQ3 SDRAM6 SDRAM7 GND V DDQ3 SDRAM16 GND V DDQ3 SDATA [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC V DDQ3 SDRAM15 SDRAM14 GND V DDQ3 SDRAM13 SDRAM12 GND OE [1] V DDQ3 SDRAM11 SDRAM10 GND V DDQ3 SDRAM9 SDRAM8 GND V DDQ3 SDRAM17 GND GND [1] S CLO CK
Note: 1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs (not CMOS level).
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
·
3901 Nor th First Street
·
San Jose
·
CA 95134
·
408-943-2600 April 5, 2001
W40S01-04
Pin Definitions
Pin Name SDRAM0:17 Pin No. 4, 5, 8, 9, 13, 14, 17, 18, 21, 28, 31, 32, 35, 36, 40, 41, 44, 45 11 24 25 3, 7, 12, 16, 20, 23, 29, 33, 37, 42, 46 6, 10, 15, 19, 22, 26, 27, 30, 34, 39, 43 38 1, 2, 47, 48 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other.
BUF_IN SDATA SCLOCK VDDQ3
I I/O I P
Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SMBus Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. SMBus clock Input: The SMBus data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply.
GND
G
Ground Connection: Connect all ground pins to the common system ground plane.
OE NC
I -
Output Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW. No Connect: Do not connect.
2
W40S01-04
Functional Description
Output Control Pins Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 1 to 5 ns. Outputs can also be controlled via the SMBus interface. Output Drivers The W40S01-04 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15. Operation Data is written to the W40S01-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1.
Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S01-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W40S01-04, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W40S01-04, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W40S01-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Refer to Cypress clock drivers.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
3
|
|
