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Details, datasheet, quote on part number:W40S11-02
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Datasheet text preview:
W 40S11- 02
SDRAM Buffer - 2 DIMM (Mobile)
Features
· Ten skew-controlled CMOS outputs (SDRAM0:9) · Suppor ts two SDRAM DIMMs · Ideal for high-performance systems designed around Intel®'s latest Mobile chip set · I2C Serial configuration interface · Skew between any two outputs is less than 250 ps · 1 to 5 ns propagation delay · DC to 133-MHz operation · Single 3.3V supply voltage · Low power CMOS design packaged in a 28-pin, 209-mil SSOP (Shrink Small Outline Package)
Key Specifications
Supply Voltages:.......... VDD = 3.3V±5% Operating Temperature:... 0 °C to +70°C Input Threshold: ........ 1.5V typical Maximum Input Voltage: ...... VDD + 0.5V Input Frequency:..... 0 to 133 MHz BUF_IN to SDRAM0:9 Propagation Delay: ........ 1.0 to 5.0 ns Output Edge Rate:....... >1.5 V/ns Output Skew: ... ±250 ps Output Duty Cycle: .......... 45/55% worst case Output Impedance: ....... 15 ohms typical Output Type: ...... CM OS rail-to-rail
Over view
The Cypress W40S11-02 is a low-voltage, ten-output clock buffer. Output buffer impedance is approximately 15, which is ideal for driving SDRAM DIMMs.
Block Diagram
Pin Configuration
SDATA SCLOCK
Serial Port
Device Control OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8
VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM8 GND VDD SDATA [1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V DD SDRAM7 SDRAM6 GND V DD SDRAM5 SDRAM4 GND OE [1] V DD SDRAM9 GND GND SCLOCK[1]
BUF_IN
SDRAM9
Note : 1. Inter nal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs (should not be relied upon for pulling up to VDD).
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
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3901 Nor th First Street
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San Jose
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C A 95134 · 408-943-2600 September 29, 1999, rev. **
W40S11-02
Pin Definitions
Pin Name SDRAM0:9 Pin No. 2, 3, 6, 7, 22, 23, 26, 27, 11, 18 9 14 15 1, 5, 10, 13, 19, 24, 28 4, 8, 12, 16, 17, 21, 25 20 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). I2C Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. I2C Clock Input: The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. G round Connection: Connect all ground pins to the common system ground plane. O utput Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW.
BUF_IN SDATA S C L OC K VDD GN D OE
I I/O I P G I
2
W40S11-02
Functional Description
Output Control Pins Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 1 to 5 ns. Outputs can also be controlled via the I2C interface. Output Drivers The W40S11-02 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15 ohms. Operation Data is written to the W40S11-02 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1. Table 1. Byte Writing Sequence Byt e Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Comm ands the W40S11-02 to accept the bits in Data Bytes 06 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S11-02 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W40S11-02, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W40S11-02, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W40S11-23 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Refer to Cypress clock drivers.
2
C o mma n d Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
3
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