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Details, datasheet, quote on part number:W40S11-23G
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Datasheet text preview:
1W 40S1 1-2 3
W40S11-23
Clock Buffer/Driver
Features
· Thirteen skew-controlled CMOS clock outputs (SDRAM0:12) · Supports three SDRAM DIMMs · Ideal for high-performance systems designed around Intel's latest chip set · SMBus serial configuration interface · Clock Skew between any two outputs is less than 250 ps · 1- to 5-ns propagation delay · DC to 133-MHz operation · Single 3.3V supply voltage · Low power CMOS design packaged in a 28-pin, 300-mil SOIC (Small Outline Integrated Circuit), 28-pin, 173-mil (Thin Shrink Small Outline Package), and 28-pin, 209-mil SSOP (Small Shrink Outline Package)
Key Specifications
Supply Voltages:.......... VDD = 3.3V±5% Operating Temperature:... 0 °C to +70°C Input Threshold: ........ 1.5V typical Maximum Input Voltage: ......VDD + 0.5V Input Frequency:..... 0 to 133 MHz BUF_IN to SDRAM0:12 Propagation Delay: ...... 1.0 to 5.0 ns Output Edge Rate:.... >1.5 V/ns Output Clock Skew: ........ ±250 ps Output Duty Cycle: .......... 45/55% worst case Output Impedance:.....15 typical Output Type: ...... CMOS rail-to-rail
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output clock buffer. Output buffer impedance is approximately 15, which is ideal for driving SDRAM DIMMs.
Block Diagram
Pin Configuration
SDATA SCLOCK
Serial Port
Device Control SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8
SOIC VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN SDRAM4 SDRAM5 SDRAM12 VDD SDATA[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V DD SDRAM11 SDRAM10 GND V DD SDRAM9 SDRAM8 GND V DD SDRAM7 SDRAM6 GND GND [1] SCLOCK
BUF_IN
SDRAM9 SDRAM10 SDRAM11 SDRAM12 Note: 1. Internal pull-up resistor of 250K on SDATA and SCLOCK inputs (not CMOS level).
Cypress Semiconductor Corporation
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3901 Nor th First Street
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San Jose
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CA 95134
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408-943-2600 April 6, 2001
W40S11-23
Pin Definitions
Pin Name SDRAM0:12 Pin No. 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12 9 14 15 1, 5, 13, 20, 24, 28 4, 8, 16, 17, 21, 25 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SMBus Data Input: Data should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. SMBus Clock Input: The SMBus data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
BUF_IN SDATA SCLOCK VDD GND
I I/O I P G
Functional Description
Output Drivers The W40S11-23 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010
capacitive load. Thus output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15. Operation Data is written to the W40S11-23 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1.
Byte Description Commands the W40S11-23 to accept the bits in Data Bytes 06 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S11-23 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W40S11-23, bit values are ignored (Don't Care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W40S11-23, bit values are ignored (Don't Care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W40S11-23 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions refer to Table 2. Refer to Cypress Frequency Timing Generators.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
2
W40S11-23
Writing Data Bytes Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 2. Data Bytes 02 Serial Configuration Map[2] Affected Pin Bit(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Pin No. 11 10 N/A N/A 7 6 3 2 27 26 23 22 N/A N/A 19 18 N/A 12 N/A N/A N/A N/A N/A N/A Pin Name SDRAM5 SDRAM4 Reserved Reserved SDRAM3 SDRAM2 SDRAM1 SDRAM0 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Reserved Reserved SDRAM7 SDRAM6 Reserved SDRAM12 Reserved Reserved Reserved Reserved Reserved Reserved Control Function Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0 Low Low Low Low Low Low Low Low Low Low Low Low Low ------Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) Active Active Active Active Active Active Active Active Active Active Active Active Active ------Bit Control 1 Table 2 gives the bit formats for registers located in Data Bytes 06.
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Note: 2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to a "0."
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