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Part: DS21Q41BTN
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
-> Framers/Mappers
Description: Quad t1 Framer
Company: Dallas Semiconductor
Datasheet: Download DS21Q41BTN datasheet File size : 93 kB
Request For quote: Find where to buy DS21Q41BTN
Datasheet text preview:
DS21Q41B Quad T1 Framer
www.dalsemi.com
FEATURES
§ § § § § Four T1 DS1/ISDN-PRI framing transceivers All four framers are fully independent Frames to D4, ESF, and SLC-96 formats 8-bit parallel control port that can be connected to either multiplexed or nonmultiplexed buses Each of the four framers contains dual twoframe elastic stores that can connect to asynchronous or synchronous backplanes up to 8.192 MHz Extracts and inserts robbed bit signaling Framer and payload loopbacks Large counters for BPVs, LCVs, EXZs, CRC6, PCVs, F-bit errors and the number of multiframes out of sync Contains ANSI 1s density monitor and enforcer CSU loop code generator and detector Programmable output clocks for Fractional T1, ISDN-PRI, Actual Size and per channel loopback applications Onboard FDL support circuitry Pin-compatible with DS21Q43 Quad E1 Framer 5V supply; low power CMOS Available in 128-pin TQFP Industrial (-40°C to +85°C) grade version available (DS21Q41BTN)
FUNCTIONAL DIAGRAM
RECEIVE FRAMER
ELASTIC STORE
TRANSMIT FORMATTER
ELASTIC STORE
§ § § § § § § § § § §
FRAMER #0 FRAMER #1 FRAMER #2 FRAMER #3 CONTROL PORT
ACTUAL SIZE
QUAD T1 FRAMER
DESCRIPTION
The DS21Q41B combines four of the popular DS2141A T1 Controllers onto a single monolithic die. The "B" designation denotes that some new features are available in the Quad version that were not available in the single T1 device. The added features in the DS21Q41B are listed in Section 1. The DS21Q41B offers a substantial space savings to applications that require more than one T1 framer on a card. The Quad version is only slightly bigger than the single T1 device. All four framers in the DS21Q41B are totally independent; they do not share a common framing synchronizer. Also, the transmit and receive sides of each framer are totally independent. The dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. The DS21Q41B meets all of the latest specifications including ANSI T1.403 (and the emerging T1.403-199X), ANSI T1.231-1993, AT&T TR62411, AT&T TR54016, ITU G.704 and G.706. 1 of 61 092299
DS21Q41B
1.0 INTRODUCTION
The DS21Q41B Quad T1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer #3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each of the four framers within the DS21Q41B maintain the same register structure that appeared in the DS2141A. The two framer select inputs (FS0 and FS1) are used to determine which framer within the DS21Q41B is being accessed. In this manner, software written for the DS2141A can also be used with only slight modifications, in the DS21Q41B. Several new features have been added to the framers in the DS21Q41B over the DS2141A. Below is short list of the new features. More details can be found in Sections 2 through 12. ADDED FEATURE Non-multiplexed parallel control port operation ANSI ones density monitor (transmit and receive sides) and enforcer (transmit side only) CSU loop code generator Elastic store reset and minimum delay mode Divide RSYNC output by two for D4 to ESF conversion applications TCLK keep alive Indications of transmit side elastic store slip direction Ability to decouple the receive and transmit elastic stores Counting of excessive 0s (EXZs) SECTION 2 3 and 4 3 3 and 10 3 3 4 10 5
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DS21Q41B
DS21Q41B BLOCK DIAGRAM Figure 1-1
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DS21Q41B
TRANSMIT PIN LIST Table 1-1
PIN 19 53 87 113 126 32 66 92 128 34 68 94 1 35 69 95 20 54 88 114 22 56 90 116 2 36 70 96 3 37 71 97 21 55 89 115 SYMBOL TCLK0 TCLK1 TCLK2 TCLK3 TSER0 TSER1 TSER2 TSER3 TCHCLK0 TCHCLK1 TCHCLK2 TCHCLK3 TCHBLK0 TCHBLK1 TCHBLK2 TCHBLK3 TLCLK0 TLCLK1 TLCLK2 TLCLK3 TLINK0 TLINK1 TLINK2 TLINK3 TPOS0 TPOS1 TPOS2 TPOS3 TNEG0 TNEG1 TNEG2 TNEG3 TSYNC0 TSYNC1 TSYNC2 TSYNC3 TYPE I I I I I I I I O O O O O O O O O O O O I I I I O O O O O O O O I/O I/O I/O I/O DESCRIPTION Transmit Clock for Framer 0 Transmit Clock for Framer 1 Transmit Clock for Framer 2 Transmit Clock for Framer 3 Transmit Serial Data for Framer 0 Transmit Serial Data for Framer 1 Transmit Serial Data for Framer 2 Transmit Serial Data for Framer 3 Transmit Channel Clock from Framer 0 Transmit Channel Clock from Framer 1 Transmit Channel Clock from Framer 2 Transmit Channel Clock from Framer 3 Transmit Channel Block from Framer 0 Transmit Channel Block from Framer 1 Transmit Channel Block from Framer 2 Transmit Channel Block from Framer 3 Transmit Link Clock from Framer 0 Transmit Link Clock from Framer 1 Transmit Link Clock from Framer 2 Transmit Link Clock from Framer 3 Transmit Link Data for Framer 0 Transmit Link Data for Framer 1 Transmit Link Data for Framer 2 Transmit Link Data for Framer 3 Transmit Bipolar Data from Framer 0 Transmit Bipolar Data from Framer 1 Transmit Bipolar Data from Framer 2 Transmit Bipolar Data from Framer 3 Transmit Bipolar Data from Framer 0 Transmit Bipolar Data from Framer 1 Transmit Bipolar Data from Framer 2 Transmit Bipolar Data from Framer 3 Transmit Sync for Framer 0 Transmit Sync for Framer 1 Transmit Sync for Framer 2 Transmit Sync for Framer 3 4 of 61
DS21Q41B
127 33 67 93 125 31 65 91
TFSYNC0 TFSYNC1 TFSYNC2 TFSYNC3 TSYSCLK0 TSYSCLK1 TSYSCLK2 TSYSCLK3
I I I I I I I I
Transmit Sync for Elastic Store in Framer 0 Transmit Sync for Elastic Store in Framer 1 Transmit Sync for Elastic Store in Framer 2 Transmit Sync for Elastic Store in Framer 3 Transmit System Clock for Elastic Store in Framer 0 Transmit System Clock for Elastic Store in Framer 1 Transmit System Clock for Elastic Store in Framer 2 Transmit System Clock for Elastic Store in Framer 3
RECEIVE PIN LIST Table 1-2
PIN 6 40 74 100 13 49 83 107 9 43 77 103 10 44 80 104 5 39 73 99 4 38 72 98 8 42 76 SYMBOL RCLK0 RCLK1 RCLK2 RCLK3 RSER0 RSER1 RSER2 RSER3 RCHCLK0 RCHCLK1 RCHCLK2 RCHCLK3 RCHBLK0 RCHBLK1 RCHBLK2 RCHBLK3 RLCLK0 RLCLK1 RLCLK2 RLCLK3 RLINK0 RLINK1 RLINK2 RLINK3 RPOS0 RPOS1 RPOS2 TYPE I I I I O O O O O O O O O O O O O O O O O O O O I I I DESCRIPTION Receive Clock for Framer 0 Receive Clock for Framer 1 Receive Clock for Framer 2 Receive Clock for Framer 3 Receive Serial Data from Framer 0 Receive Serial Data from Framer 1 Receive Serial Data from Framer 2 Receive Serial Data from Framer 3 Receive Channel Clock from Framer 0 Receive Channel Clock from Framer 1 Receive Channel Clock from Framer 2 Receive Channel Clock from Framer 3 Receive Channel Block from Framer 0 Receive Channel Block from Framer 1 Receive Channel Block from Framer 2 Receive Channel Block from Framer 3 Receive Link Clock from Framer 0 Receive Link Clock from Framer 1 Receive Link Clock from Framer 2 Receive Link Clock from Framer 3 Receive Link Data from Framer 0 Receive Link Data from Framer 1 Receive Link Data from Framer 2 Receive Link Data from Framer 3 Receive Bipolar Data for Framer 0 Receive Bipolar Data for Framer 1 Receive Bipolar Data for Framer 2 5 of 61
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