Details, datasheet, quote on part number: DDU8F-5150B1
CategoryTiming Circuits => Delay Lines
Description5-tap, Ttl-interfaced Fixed Delay Line
CompanyData Delay Devices, Inc.
DatasheetDownload DDU8F-5150B1 datasheet


Features, Applications


Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability

The DDU8F-series device a 5-tap digitally buffered delay line. The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time an T1-T5 Tap Outputs amount determined by the device dash number (See Table). For dash VCC +5 Volts numbers less than 5025, the total delay of the line is measured from T1 to GND Ground T5. The nominal tap-to-tap delay increment is given by one-fourth of the total delay, and the inherent delay from T1 is nominally 3.5ns. For dash numbers greater than or equal to 5025, the total delay of the line is measured from to T5. The nominal tap-to-tap delay increment is given by one-fifth of this number.

Minimum input pulse width: 40% of total delay Output rise time: 2ns typical Supply voltage: 5% Supply current: ICCL = 32ma typical ICCH = 7ma typical Operating temperature: 70 C Temp. coefficient of total delay: 100 PPM/C

* Total delay is referenced to first tap output Input to first tap 1ns NOTE: Any dash number between 5004 and 5250 not shown is also available.

The DDU8F tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small 40% of the total delay and periods as small 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.

The DDU8F relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used.

PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VCC VIN TSTRG TLEAD MIN -0.3 -55 MAX 150 300 UNITS NOTES

to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short-circuit Output Current Output High Fan-out Output Low Fan-out SYMBOL VOH VOL IOH IOL VIH VIL VIK IIHH IIH IIL IOS MIN 2.5 TYP 3.4 0.35 MAX UNITS A mA Unit Load NOTES VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX


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