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Details, datasheet, quote on part number:DD-00429FP
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DD-00429
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ARINC 429 MICROPROCESSOR INTERFACE
FEATURES
· Four ARINC 429 Receive Channels, (configured with Transceivers) · Two ARINC 429 Transmit Channels (configured with Drivers) · 128 x 32 Shared RAM Interface · Label and Destination Decoding and Sor ting · Two 32 x 32 Transmit FIFO's · Four 32 x 32 Receive FIFO's · Interfaces Easily to 8- or 16-Bit Microprocessor
DESCRIPTION
DDC's DD-00429 provides a complete and flexible interface between a microprocessor and an ARINC 429 data bus. The DD-00429 interfaces to a processor through a 128 x 32 bit static ram as well as four 32 x 32 receive FIFOs and two 32 x 32 transmit FIFOs. The DD00429 can be easily interfaced to 8- or 16-bit processors via a buffered shared RAM configuration. The DD-00429, when configured with two Transceivers, supports four ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) each receiving data independently. The receive data rates (high or low speed) for channel Rx0 and Rx1 can be programmed independently from Rx2 and Rx3. The DD-00429 can decode and sort data based on the ARINC 429 Label and SDI bits via the Data Match Processor, and store it in RAM and/or FIFOs via the Data Store Processor. The DD-00429, when configured with two Line Drivers, supports two ARINC 429 Transmit channels (Tx0 and Tx1) and can transmit data independently. The transmit data rate can also be programmed independently. There are two 32 x 32 bit FIFOs for each of the transmitters that send out data. The DD-00429 has the capability of programming three general purpose interrupts as well as generating an interrupt based on an error condition. The general purpose interrupts can be programmed to trigger other external hardware. They can either be LEVEL or PULSE driven. The features built into the DD-00429 enable the user to off-load the host processor and use that processing time to implement operations other than polling the ARINC 429 Bus. The decoding and sorting of data allows the user to gather data much quicker than past designs. If the user requires a microprocessor in the avionics box, this device will facilitate a clean and quick design.
Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
· Built-in Fault Detection Circuitry · Free "C" Librar y Software · Application Note AN/A-6 "FAQ's"
FOR MORE INFORMATION CONTACT:
Technical Support: 1-800-DDC-5757 ext. 7234
All trademarks are the property of their respective owners. © 1998, 1999 Data Device Corporation
Data Device Corporation www.ddc-web.com
128 X 16 STATIC RAM DMT RAM
CTRL DATA ADDR
128 X 32 STATIC RAM Rx RAM
CTRL DATA ADDR
ARINC 429 RECEIVE 0
WRAPAROUND
ARINC 429 Rx0 LOGIC DMP DATA ADDR
Rx0 FIFO 32 WORDS
A 1OUT
B 1OUT
DD-03182 LINE DRIVER
ARINC 429 RECEIVE 1
WRAPAROUND
ARINC 429 Rx1 LOGIC ARINC 429 Rx2 LOGIC
Rx DATA
ARINC 429 RECEIVE 2
DATA MATCH PROCESSOR
DATA ADDR
DATA STORE PROCESSOR
DATA ADDR
Rx1 FIFO 32 WORDS
WRAPAROUND
Rx2 FIFO 32 WORDS
ARINC 429 RECEIVE 3 A 2O U T
WRAPAROUND
B 2OUT
DD-03182 LINE DRIVER
ARINC 429 Rx3 LOGIC
ADDR DATA DATA
Rx3 FIFO 32 WORDS
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ARINC 429 TRANSMIT 0
2
ARINC 429 Tx0 LOGIC
Tx FIFO 32 WORDS
DATA
ARINC 429 TRANSMIT 1
2 ARINC 429 Tx1 LOGIC Tx FIFO 32 WORDS
INTERRUPT CONTROLLER
3
CPU INTERFACE
16 12
IRQ
DATA
ADDR
CONTROL
MICROPROCESSOR OR CPU
DD-03182 LINE DRIVER (x2)
DD-03282 TRANSCEIVER (x2)
DD-00429 FP/VP ASIC
FIGURE 1. CHIP SET BLOCK DIAGRAM
TABLE 1. DD-00429 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER DC Supply Voltage Signal Input Voltage (logic inputs) Storage Temperature Operating Temperature Lead Temperature (soldering) Body Temperature (soldering) MIN -0.3 -0.3 -85 -40 MAX 7.0 Vdd+0.3 125 85 280 (for 3 sec) 210 (for 30 sec) UNITS Vdc Vdc °C °C °C °C
TABLE 2. DD-00429 SPECIFICATIONS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER LOGIC INPUTS/OUTPUTS DC Supply Voltage DC Supply Current Schmitt "0" Threshold Schmitt "1" Threshold Schmitt Hysteresis Input Logic Voltage Low Input Logic Voltage High Input Logic Current Low Vdd Idd VtVt+ Vh Vil Vih Iil 2.0 -25.3 -137 0.8*Vdd 1 0.8 4.5 5.5 42.2 0.2*Vdd Vdc mA Vdc Vdc Vdc Vdc Vdc µA Device operation @ 16 MHz, Typical Idd = 38.4 mA @ 5.0V. (@85°C) RESET RC*, 16 MHZ CLOCK RESET RC*, 16 MHZ CLOCK RESET RC*, 16 MHZ CLOCK All other Inputs. (See Note 1). All other Inputs. (See Note 1). Input pins with internal pull-up logic: INT/MOT*, 8/16*, ZERO WAIT MODE and MASTER RESET* @ Vdd = 5.5V All other Inputs. (See Note 1). All other Inputs. (See Note 1). Io1=3.84 mA minimum @Vdd= 4.5V. (See note 2) Ioh=3.84 mA minimum @Vdd= 4.5V. (See note 2) For TXDB0-TXDB15, D0-D15, READY, DTACK*, ERROR*, IRQ3*, IRQ2* and IRQ1 @ vdd = 5.5V SYMBOL MIN MAX UNITS COMMENTS
Input Logic Current Low Input Logic Current High Output Voltage Logic Low Output Voltage Logic High Output Leakage Current, Hi-Z
Iil Iih Vol Voh Ioz
-1.0 -1.0
1.0 1.0 0.4
µA µA Vdc Vdc
2.4 -10 10
µA
NOTES: 1. TTL compatible input logic voltage levels at CMOS input logic current levels. 2. CMOS output logic voltage at current levels.
ARINC 429 RECEIVERS
The DD-00429 supports four ARINC 429 inputs, designated Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The architecture of each of the four receiver circuits is identical and each receives data independently. ARINC 429 data is directly received into the ARINC 429 transceiver. Input protection, in accordance with the ARINC 429 specification, is provided along with voltage level translation from +5 V bipolar, nonreturn-to-zero data to conventional, +5 V logic levels. Data Device Corporation www.ddc-web.com
Receive Data Rates: Data rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of Arinc Control Register 2. The receiver circuitry will successfully decode an incoming ARINC 429 data stream as long as the data rate is within ±5% of the nominal rate as determined by the Hi Speed/Low Speed Bit and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or may be connected to another clock source.
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The ARINC CLK input should nominally be 10 times (for HighSpeed Mode) or 80 times (for Low-Speed mode) the desired ARINC Data Rate. ARINC CLK 0 is used to synchronize channels Rx0 and Rx1 while ARINC CLK 1 is used to synchronize channels Rx2 and Rx3. Filtering and Sorting Rx Data: The receiver circuitry converts the serial data stream into a 32-bit-wide parallel data word. The 32-bit word is processed internally by a Data Match Processor (DMP). It compares the incoming data to a table of data initialized by the processor. This determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. The table of data is stored in a 128 word x 16 bit Data Match Table (DMT) RAM. When a match between the received ARINC 429 data and the criteria stored in a DMT entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the Data Store Processor (DSP). The storage address in the Receive RAM is the address of the first matching DMT entry minus 200 hex. There are three requirements that must be met in order to match incoming ARINC 429 data to each DMT entry: 1) System Address Label: Bits 0-7 of the DMT are compared to the System Address Label (SAL) of the incoming ARINC 429 data word. If the DMT SAL entry is zero then the SAL of the incoming data word is ignored (or considered a match). 2) Source/Destination Bits: Bits 8 and 9 of each DMT entry are compared to the Source/Destination (S/D) bits of the incoming ARINC 429 data word. If these bits match, or if Bit 10 of the DMT entry is set to a 1, then the S/D bit comparison is considered a match. It is also possible, through DMP Control Register 1, to enable "All Call Mode" as defined in the ARINC 429 specification. When enabled for a particular receive channel, the S/D bits will be considered a match when the incoming ARINC 429 data contains a 00 in its S/D bit pair. 3) Receive Channel Number: Bits 12 and 13 of each DMT entry are compared to the number of the channel which received the ARINC 429 data. A Data Match has occurred when all of the previous conditions are satisfied; the data will then be stored in a RAM location whose address equals the matching DMT entry minus 200 hex. Bit 11 of each DMT entry, when set, will cause the incoming ARINC 429 data to be stored in the corresponding receive channel FIFO (as well as the Rx RAM) when the data match conditions are met. Bits 14 and 15 of each DMT entry provide the ability to cause one of three general purpose interrupts upon a data match condition. If set to "00" then no interrupt will occur upon a data match condition (more information on interrupts is described later). Data Device Corporation www.ddc-web.com
ARINC 429 TRANSMITTER(S)
The DD-00429 supports two ARINC 429 transmitters. Each of these channels transmits data independently and are designated Tx0 and Tx1. The transmit output of the DD-00429 is a TTL encoded digital data stream which can be connected directly to the ARINC 429 line driver. Transmit Data Rates: Data rates can be programmed for Channels 0 and 1 independently. The transmit data rate is determined by the High-Speed/Low-Speed Bit for each of the Tx channels in Arinc Control Register 1 and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two, 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or they may be connected to another clock source to achieve transmit data rates other than 100 kHz or 12.5 kHz. The transmit clock input should be 10 times (for High-Speed Mode) or 80 times (for LowSpeed mode) the desired ARINC transmit data rate. Transmit FIFOs: Each transmitter channel is provided with an output FIFO which is 32 words deep by 32 bits wide. When writing data to the Tx FIFO, the associated Disable Tx(n) bit in ARINC Control Register 2 can be set to a logic zero until the FIFO is loaded with the desired data. Upon setting the Disable Tx(n) low the transmit channel will send the 32-bit message words with appropriate interword gaps on the ARINC 429 output. A status bit indicating that the FIFO is empty is supplied for each transmitter in the ARINC Status Register. Wraparound testing can be performed from Tx0 to Rx0 and Rx1, and from Tx1 to Rx2 and Rx3. The data received on Rx1 and Rx3 in wraparound test mode is inverted. Wraparound testing is enabled by setting the appropriate bits in Arinc Control Register 1. The parity of the transmitted word can be altered to no parity (instead of the usual odd parity) by setting the associated Tx(n) Parity bit in the Arinc Control Register 1. This is useful to verify proper operation of the parity check circuitry for each of the receive circuits during wraparound test mode.
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PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16bit data bus. Intel or Motorola control signal formats can also be used.
ZERO WAIT MODE OPERATION
When Zero Wait Mode is enabled by not grounding the ZERO WAIT pin, the host microprocessor may read data from the DD00429 shared memory resources (DMT and Rx RAM) without using the READY or DTACK signals to insert wait states into the microprocessor cycle. This is accomplished by an additional "dummy read" of the desired address. This dummy read causes the DD-00429 to fetch the data from the source and place it in a latch. The data can then be read from the latch (word-by-word or byte-by-byte) by reading the same addresses. Thus for a 32-bit read in 8-bit mode, the microprocessor would perform a total of five read operations. The first read would be the dummy read; subsequent reads would transfer the data.
INTERRUPT OPERATIONAL MODES
The DD-00429 provides four interrupt outputs. Three of these interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose programmable interrupts. The fourth interrupt is an Error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low to indicate the presence of an error. The error pin will go high again when the Error Status Register is clear. Each of these bits is cleared by either reading the Error Status Register or removing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for multilevel interrupts or to trigger other external hardware for various conditions. Each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to IRQ0 which does not exist). Each interrupt output can be programmed to be either a LEVEL interrupt or PULSE interrupt via the associated IRQ Control Register 2. When programmed for pulse interrupt mode, the associated interrupt pin will go low for 1 µS and return high again. When programmed for LEVEL interrupt mode, the interrupt will remain until the associated IRQ Status Register is read, thus clearing the associated bits in each interrupt register. Each of the individual interrupt registers can be masked by setting their corresponding bit in IRQ Control Register 1. It should be noted that the masking function only prevents the associated IRQ pin from becoming active. When the mask bit is cleared, an interrupt can occur in LEVEL IRQ mode if one or more interrupt conditions occurred during the time when the mask was set. If the user needs to ensure the interrupt will not occur upon clearing the mask bit, the CPU should be programmed to read the associated interrupt status register immediately prior to clearing the IRQ mask bit.
Data Device Corporation www.ddc-web.com
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