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Details, datasheet, quote on part number:DD-03296
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Datasheet text preview:
DD-03296
96-CHANNEL DISCRETE-TO-DIGITAL INTERFACE
FEATURES
DESCRIPTION
The DD-03296 device is a 96-channel discrete-to-digital interface with universal HlRF-isolated inputs that accept 28 V/Open, Open/Gnd and 28 V/Gnd signals. The output is an addressable 8- or 16-bit tri-state port, selectable for channel data, status, bounce, built-in self-test (BIST) and major fault, and is compatible with TTL logic.
APPLICATIONS
The DD-03296 is specifically designed to address built-in self-test autonomy, fault isolation and tolerance. Because of its high reliability and low cost, these features enable the DD03296 to satisfy a variety of interface requirements in aerospace applications, including flight critical, essential, and nonessential functions.
· HIRF Layer · Universal Inputs
28 V/Gnd Open/Gnd 28 V/Open
· Built-in Self-Test · Soft Failure Reporting
Higher MTBUR
· ARINC 429 Output Port
REFERENCE INPUT
DATA 96 BOUNCE 96 REFERENCE INPUT PROCESSOR AND DISCRETE 96 BIT TEST MATRIX INPUTS 96 FAULT 96 ENABLE HI 5 MATRIX SHIFT H/L TEST DISCRETE TRANSFER ENABLE LO 5 ADDRESS 3 3 DISCRETE DATA EN DECODER ARINC DATA EN SEL0 SEL1 SEL2 1 MHZ RESET* DUAL REDUNDANT CLOCK AND CONTROL LOGIC
DISCRETE TRI-STATE DRIVERS
16
DATA BUS
DATA (8/16 BITS)
DISCRETE DATA TRANSFER VERIFIER
TRANSFER FAULT FAULT PROCESSING CIRCUITRY
96
96 TRANSFER FAULT ENABLE* ADDRESS (A5..A0) 8/16 BUS ARINC DATA TRANSFER VERIFIER
FAULT BIT
FAULT*
DISCRETE FAULT
ARINC FAULT
16 ARINC 429 TRI-STATE DRIVERS
DATA BUS
TRI-STATE ENABLES 2 ARINC 429 XMITTER READY 10µS CLOCK 80µS CLOCK
(TTL) ARINC 429 OUTPUT
ARINC 429 DATA RATE ARINC 429 MESSAGE RATE
DATA READY NOTE: (*) Indicates active low.
FIGURE 1. DD-03296 BLOCK DIAGRAM ©
1993, 1999 Data Device Corporation
U.S. Patent No. 5526288
TABLE 1. DD-03296 SPECIFICATIONS PARAMETER UNITS MlN TYP MAX ABSOLUTE MAXIMUM RATINGS Supply VoItages (VCC, VDD) V -0.3 5.0 7.0 Reference Inputs V -80 80 80 Discrete Inputs V -80 VDD+0.3 Digital Inputs V -0.3 OPERATING CONDITIONS Supply Voltages (VDD) V 4.5 5.5 DIGITAL INPUTS/OUTPUTS Logic Compatibiliy TTL/ CMOS Digital Inputs s VIH V 2.0
sVIL sVIL (VIN
WHAT IS A DISCRETE?
Advisory Circular (FAA), Airworthiness Approval of Traffic Alert and Collision Avoidance Systems (TCAS II) and Mode S Transponders, AC20-131, defines a discrete as "a separate, complete and distinct signal. " In many instances these signals are binary, on or off, 28 V-based signals; they are typically Open/Gnd, 28 V/Open, or 28 V/Gnd with very low bandwidth (DC to 200 Hz). Although the translation of these signals to TTL-levels that are compatible with digital avionics may seem simple, RTCA DO160 power, lightning and high-intensity-radiated-fields (HIRF) are complicating factors. Add to that the desire to have a standardized, addressable, reliable interface and the challenge becomes apparent. Today's systems address the interface requirements with circuits tailored for each interface comprised of R-C input filters, divider networks, diode isolation and comparators. Multichannel interfacing to a processor requires additional logic and latches. The resulting circuit generally lacks any built-in test capability, consumes considerable pc-board real estate (up to one sq. in. per channel) and offers no chip-level redundancy.
V = 0) µA MHz V V V See FIGURE 4 -40 0.99 VDD-0.5 2.4 1.00
0.8 -400 1.01
Clock Input (See Note 1) Digital Outputs sVOH (lOH = -1ma)
sVOH sV L O
(IOH = -4ma) (lOH = 4ma)
0.4
ANALOG INPUTS POWER SUPPLY REQUIREMENTS (Total VDD, Analog & Digital) IDD (VDD = +5V [Digital Outputs Unloaded]) POWER DISSIPATION PD THERMAL Operating Temperature sType 2 Storage Temp Lead Temperature (Localized, 1 sec. duration) (Body, 2 sec. duration) Junction Temperature jc ca MTBF per Mil-Hbk-217 for Airborne Inhabited Cargo at 64°C PHYSICAL CHARACTERISTICS Size Weight
mA
25
45
FUNCTIONAL INTEGRATION
mw 125.0 250.0
°C °C °C °C °C/W °C/W
-40 -65
85 150 280 210 5.0 20.0
Using the aggregated signal definition and functional requirements of industry, ILC Data Device Corporation has developed a discrete interface with universal HIRF-isolated inputs to handle 28V/Open, Open/Gnd and 28V/Gnd signals. Each channel is routed through a HIRF filter and comparator. Its output is a selectable 8- or 16-bit tri-state port, addressable for channel data, status, bounce, built-in self-test and major fault information. This design specifically addresses built-in self-test autonomy, fault isolation and tolerance; moreover, its functional integration results in significant added reliability. A comparative look at MTBF, calculated in accordance with MIL-HBK-217 for airborne inhabited cargo environments at 64°C, indicates an order of magnitude improvement (1,400,000 hours vs. 173,000 hours) for a plastic packaged integrated approach vs. a similarly packaged discrete-component implementation. In addition, the real estate used is reduced from as much as 64 to 5 square inches. Additional key DD-03296 features include:
1,400,000 hrs. plastic in (cm) oz (gm) 2.3 x 2.3 (5.84 x 5.84) 0.83 23.5
Note 1: ARINC 429 bit rate is derived from the clock. Refer to ARINC 429 Bit Rate to avoid interference. ARINC 429-14 (January 4, 1993), paragraph 2.4 "Timing Related Elements" contains a "COMMENTARY" section following subparagraph 2.1.4.2 ("Low-Speed Operation") that cautions against using "precisely" 100 kilobits per second.
BOUNCE: Relays and switches, as mechanical devices, have a characteristic `bounce' to their signal transition. It is desirable to mask this bounce by delaying the output digital transition accordingly. This sampling rate of the device can be varied to allow for debounce of relay/switch inputs. In addition, the triplesampling of a given comparator enables a consistent reading of otherwise asynchronous signals. Bounce is an addressable sta-
2
tus that allows the user to detect bouncing or intermittent relays/switches.
sented to the device. The addressed data will be available within 100 nsec. After the data is read, the ENABLE line should be returned to a logic "1" level before the address is changed. All of the data within the device is guaranteed to remain stable for at least 20 µsec after the high-to-low transition of the READY signal (See FIGURE 3).
GROUND DIFFERENTIALS: When the reference inputs are connected to the 28V supply, the thresholds are designed to tolerate ±3.5V ground differences. REGISTERS: 8- or 16-bit selectable data or status are available via tri-state buffers for interfacing to any system processor. ARINC 429 PORT: A serial ARINC 429 output is available for data-concentrator applications. This enables the transfer of data to other systems with a minimum of wiring and processor loading. HIRF: The device incorporates passive circuitry to isolate the intelligence from both lightning effects and radiated fields as defined in DO-160. This protection is applicable to the discrete inputs, reference inputs and their relationship to each other and to ground. TEST PATTERNS: Internal Test Patterns can be selected to produce alternating "1"s and "0"s to verify that all address and data bits are operational. While these outputs are always available, regardless of READY state, they must be addressed by the user (A5... A0) in accordance with TABLES 3 and 4. DISSIMILAR PATHS: Errors are reported through registers and the ARINC 429 port as cross-checks. INTELLIGENCE: The device's built-in self-test, status reporting scheme and isolation significantly reduces application software requirements. FIGURE 1 illustrates the model DD-03296 functional block diagram. ASYNCHRONOUS SAMPLING: The device takes three samples on each encode because input discrete transition is asynchronous and reports the "majority" state.
ANALOG INPUTS
ANALOG INPUT CHANNELS: (Pins 161, 162, 1-6, 8-15, 19-26, 29-36, 45-52, 55-62, 66-73, 76-83, 85-92, 95-102, 105-112, 115-122) 600k input resistance, 500µs time constant, responsive to Open/Gnd (when configured with appropriate external pull-up), 28V/Open and 28/Gnd input with HIRF/lightning immunity. Refer to FIGURE 4 for detail of the input structure. REFERENCE: Configured for 28V tracking discretes. User adjustable for other reference levels by connecting external resistors between corresponding TRIM and REF inputs.
FIGURE 4 also shows the reference structure. Each set of Ref/Trim inputs are configured by the user for a bank of 32channel inputs. (See FIGURE 4 and TABLE 8)
REF A, B, C: (Pins 37, 65, and 75) Input to the divider supplying the reference voltage to the "A," "B" and "C" group of 96 input channels. TRIM A, B, C: (Pins 38, 64, and 74) Junction of the first resistor and the rest of the reference "A," "B" and "C" divider.
DIGITAL INPUTS
DEBOUNCE (SEL2...SEL0): (Pins 158-160) The Input Discrete Sampling Rate (Debounce Time) is user-programmable via the three Select lines (SEL2...SEL0) in accordance with TABLE 2. The intent of this function is to mask the bounce of the input dis-
MICROPROCESSOR INTERFACE READ CYCLE TIMING
TABLE 2. DISCRETE SAMPLING RATE
The DD-03296 is configured with either an 8- or 16-bit microprocessor. FIGURE 2 illustrates this interface. The read cycle(s) should be preceded by polling the device's READY bit located within the Status Register. The Status Register can be read at any time regardless of the state of the READY signal (pin 16) from the device. If the READY bit is a logic "1" (this can be easily tested by a branch if negative statement), the address of the desired register, along with the negative true ENABLE signal, should be pre3
SELECT (SEL 2 . . SEL 0) 000 001 010 011 100 101 110 111
SAMPLE RATE 5 msec 10 msec 20 msec 50 msec 100 msec 200 msec 500 msec 1000 msec
+5V
D15..D0 Chan 1..96 A5..A0 Ref A, B, C Sel 2..0
DD-03296
READY Enable 8/16* Bits
CPU
1 MHz CMOS Clock Osc.
* indicates active low signal
NOTE: 1) If 8/16* Bits pin is tied to +5V, then the DD-03296 is configured for 8-Bit Mode. The following must also be modified: D0 tied to D8 D1 tied to D9 D2 tied to D10 D3 tied to D11 D4 tied to D12 D5 tied to D13 D6 tied to D14 D7 tied to D15 2) If the ARINC 429 option is not used, then pin 153 (429STRBI) MUST be grounded for the "bounce" circuit to operate properly.
FIGURE 2. DD-03296-TO-CPU INTERFACE
Ready
TRA
10 ns Min (See Note 3)
Address TAE Enable* 10 ns Min TEA - 10 ns Min
TED Data
TEDOFF 100 ns Min
50 ns Min
TAVAIL
20 µs
Note: 1) TRA = Time Ready Address 2) TAE = Time Address Enable 3) TEA = Time Enable to Address 4) TED = Time Enable Data 5) TEDOFF = Time Enable Off - Data Off 6) TAVAIL = Time Ready* - Data Available 7) (*) Indicates active low. 8) The ready "on-time" = (sample rate - 440 µs) Sample rate is programmable via SEL0 - SEL2 (See TABLE 2)
FIGURE 3. READ CYCLE TIMING
4
crete appropriate to its characteristic performance. See BOUNCE on page 2.
ENABLE: (Pin 147) The ENABLE line controls the tri-state drivers of the 8- or 16-bit Data Bus outputs. The tri-state Data Bus drivers are enabled when this signal is a logic "0," and are tristated when this signal is a logic "1." ENABLE is a read signal and should only be low during read cycles. 8 /16 BITS: (Pin 104) A logic "0" selects the 16-bit data bus output and a logic "1" selects the 8-bit data bus output. ADDRESS LINES (A5...A0): (Pins 139, 140 and 143-146) The six address lines (A5... A0, where A0 is the LSB) provide for the selection of the desired 8- or 16-bit Data Bus information in accordance with TABLE 3 and TABLE 4 (Word/Byte Modes). CLOCK (1MHZ CLK): (Pin 28) The user must supply a 1 MHz clock whose stability is of no importance except to the serial bit rate of the ARINC 429 port (see Note 1 of TABLE 1). The clock is brought into the internal ASIC at two widely separated points designated as CLOCK_A (primary) and CLOCK_B (secondary) path.
The primary clock path will be selected and drive the device unless a primary clock path fault is detected, in which case the operation of the device will get switched over to the secondary clock path. Both clock paths are continually monitored for status and this information is available as separate bits in the Status Register.
FACTORY TEST INPUTS: (Pins 39, 40, 149 and 150) The TMUX, TMODE, FMUX and FMODE input signals are used for factory testing and should be tied to logic "1" for the device to operate properly. RESET: (Pin 41) The RESET signal is used to reset the device during factory testing. It may be connected to an external RC network to provide a Power-on-Reset for the device. Under normal operating conditions this pin should be a no-connect. If there is some reason to reset the device from external circuitry this pin can be momentarily pulled to logic "0" through an open collector device. Do not hard wire this pin to +5V or ground.
OUTPUTS
DATA (D15...D0): (Pins 123-138) 8-bit byte or 16-bit byte word information is available on the Data Bus depending on the logic state of the Bus Select line as described above.
In the Byte mode the upper and lower bytes are enabled separately so that bit 0 can be hard-wired to bit 8, bit 1 to bit 9 etc., thereby providing an 8-bit data bus. It is important that the 8-bit mode be selected if these data bits are wired together or corrupted data will result. The available data can be found under the Address Lines section found on page 5.
FAULT: (Pin 148) The FAULT flag was designed to serve as an interrupt to the microprocessor when a HARD error has been detected within the device (See Note 2 of TABLES 3 and 4). If this
600k CHANNEL N INPUT COMPARATOR 60k .01 µf
+ OUTPUT TO LOGIC TO OTHER COMPARATORS
93.3k REF A
1.0k
5.72k TRIM A
.1 µf
IDENTICAL REFERENCE STRUCTURE FOR REF B AND REF C
FIGURE 4. DD-03296 INPUT STRUCTURE
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