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Details, datasheet, quote on part number:PC-411/412
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PC-411/412
16-Channel, Analog I/O Boards with FIFO for IBM-PC Computers
PRODUCT DATA
FEATURES · 16SE or 8D analog input channels, expandable to 256 · 4 Analog output channels optional (PC-412) with simultaneous update · Choice of 12, 14, or 16-bit A/D resolution · On-board programmable trigger clock · Discrete digital I/O (8 input, 8 output) · FIFO memory, DMA, and programmable interrupts for continuous, non-stop, "streaming" data acquisition · Programmable gain amplifier · Signal conditioning per channel Offering non-stop continuous collection of up to 16 analog input signals in real time, the PC-411 is an analog input board for IBM-PC, PC/XT, PC/AT, and compatible computers. The PC-411 accepts 16 single-ended or 8 differential input signals, digitizes them up to 12, 14, or 16-bit resolution and places them on the computer bus under software control. Data may then be stored in PC memory, saved on disk, or displayed on the screen or printer. Model PC-412 is a combination analog input and output board using the same input section as the PC-411. The PC-412 adds four optional analog output channels to be used for chart recorders, actuator controllers, or other output devices. Both the PC-411 and PC-412 accept external analog input expansion channels. On both the PC-411 and PC-412, sixteen discrete digital I/O lines are configured as 8 inputs and 8 outputs for external logic devices. The digital outputs can control the channel addressing of an expansion input multiplexer. The differential analog inputs offer rejection of common mode noise while the on-board Programmable gain amplifier (PGA) offers higher gains (up to times 100) for low-level sensors. Onboard circuit pads on each channel may be configured for other input voltage or current ranges or input signal conditioning. Analog-to-digital converter (A/D) data passes to an on-board
INPUT EXPANSION
First-In, First-Out (FIFO) data memory. FIFO data is then transferred to the host computer bus interface under software control. Besides temporarily storing a block of samples, the FIFO acts to decouple the precise timing of the A/D section from the block-oriented data transfer burst on the bus. Unlike many other analog input boards for the PC, the PC-411/412 can continuously collect analog data with nonstop converter triggering while data is simultaneously read by the PC from the FIFO. This allows the collection of "seamless" signals of millions of samples or greater. Another advantage of the FIFO is high-speed disk recording of analog data with no loss of samples during disk writes. Expansion up to 256SE/128D total channels is offered on DATEL's PC-440 MUX board in increments of 32SE/16D channels. The timing section controlling the sampling A/D converter is designed for accurate multi-scan data acquisition. Software programmable timers control the interval between each conversion and each multichannel scan. A programmable sample counter will allow sample blocks of specified length
16SE or 8D ANALOG INPUTS
R GAIN M U X Reference Test MUX Enable Empty Channel Address Sequencer 1MHz Half Full Programmable Gain Amplifier Sampling A/D Converter EOC
EXTERNAL A/D CLOCK IN
Signal Conditioning Pads
Reset
FIFO Memory
EXTERNAL TRIGGER IN
Trigger Select 31.25 kHz
Trigger Timer (2)
Sample Counter (0)
A/D Start Timer (1) 82C54
CLK Start A/D OUT
DIGITAL I/O (8 IN, 8 OUT)
EOC Simultaneous Update
EOS
Control Registers
4 ANALOG OUTPUTS (PC-412 only)
D/A Converters
I/O Bus Interface
Base Address Select
Interrupt and DMA Request IRQ DMA T/C DRQ
Power Regulators
+5V
+12V
-12V
PC BUS
Figure 1. PC-411/412 Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · Email: sales@datel.com · Internet: www.datel.com
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PC-411/412
independent of FIFO length. The timer/counter section uses an internal clock or an external timebase. The external trigger may be used to precisely synchronize sampling with external events. The trigger may start a single sample, a single multi-channel scan, or "N" multiple scans separated by programmable delays. Either an interrupt, DMA Request, or status flag indicates when FIFO data is ready. Normally, a FIFO interrupt from the PC-411/412 triggers the PC to burst a fixed-length block of samples to host PC memory. This offers very high overall system speed by not tying up the bus and allows the PC to continue with graphics, math, or disk activities. The PC-412 analog output channels include a simultaneous update option where all channels drive their outputs to new values at the same time from a software trigger. Applications for this include phase-synchronous system simulation, process control, and coherent field waveform generation. Most options are software configured, reducing the number of jumpers required. Window-driven software is available on MS-DOS disks to configure the board and save data. A comprehensive user's manual is also included. FUNCTIONAL SPECIFICATIONS (Typical at +25°C, dynamic conditions, unless otherwise noted) ANALOG INPUTS Number of Channels (software selectable) Input Channel Expansion 16SE or 8 diff. channels External single-ended or differential analog inputs may be accepted using DATEL's PC-440. Input characteristics are identical to the on-board inputs. Non-isolated 0 to +5V, ±5V (software selectable). Other voltage and current ranges are available with user-installed precision resistors. 100 m, power on, 1.5 K, power off ±200 pA 15 pF per channel ±12V max. (no damage) 5 µs ±5V to analog common 80 dB, dc to 60 Hz, gain = 100 1 to 100 gains, selectable by precision gain resistor (pads provided) 6 µs to 0.01% (gain = 1) 15 µs to 0.02% (gain = 10) 80 µs to 0.1% (gain = 100) A/D CONVERTER CONT. Output Coding Positive-true, left-justified, straight binary (unipolar) or offset binary (bipolar) 1. Local Pacer sample clock 2. External digital sample clock 1. Single channel 2. Sequential with autosequenced addressing 3. Random addressing by host software
Trigger Sources (software-selectable) Addressing Modes
INPUT SYSTEM PERFORMANCE Integral Nonlinearity ±0.05% of FSR (411/412A) ±0.015% of FSR (411/412B) ±0.005% of FSR (411/412C) ±0.5 LSB (±1 LSB 411/412B,C) ±0.1 LSB per °C (411/412A) ±0.3 LSB per °C (411/412B,C) No missing codes ±0.01% of PC bus ±12V 17 µs (411/412A) 23 µs (411/412B) 42 µs (411/412C) (see Notes) 12 µs (PC-411/412A) 17 µs (PC-411/412B) 37µs (PC-411/412C)
Differential Nonlinearity Full Scale or Zero/Offset Temp. Coefficient Monotonicity Power Supply Rejection Total Scan Throughput (sample-to-sample with sequential addressing) Total Throughput (no channel advance) A/D MEMORY Architecture Memory Capacity TRIGGER CONTROL Programmable Timer/ Counter Type Functions
Input Configuration Full Scale Input Ranges (gain = 1)
First-In, First-Out (FIFO) 512 A/D samples
Input Impedance Input Bias Current Input Capacitance Input Overvoltage Overvoltage Recover Time Common Mode Voltage Range Common Mode Rejection Programmable Gain Amplifier
Sample Counter A/D Start Clock Source (software programmable) Trigger Source (user-selectable) Internal Trigger Range (software programmable) ANALOG OUTPUT
PGA Settling Delay
82C54 1. EOC sample count 2. A/D start rate (16-bit divisor) 3. Scan or frame rate (16-bit divisor) 1 to 65,536 samples. Drives the acquire flag/interrupt. Internal crystal clock. Range 500 KHz to 15.26 Hz (16stage binary divider or BCD) 1. Internal crystal clock 2. Ext. digital input. TTL levels, triggers on falling edge 15.625 KHz to 2.097 sec. (16stage binary divider or BCD)
A/D CONVERTER Resolution 12 bits (PC-411/412A) 14 bits (PC-411/412B) 16 bits (PC-411/412C) 7 µs (PC-411/412A) 14 µs (PC-411/412B) 32 µs (PC-411/412C) 25 ns 3 µs
Number of Channels Resolution Output Voltage Range
A/D Conversion Period
Aperture Time Acquisition Time
Output Current Nonlinearity Settling Time (full scale step) Input Coding Temperature Coefficient
4 channels, single-ended 12 bits ±5V, jumper selectable per channel (0 to 10V, ±10V special order) ±5 mA, short circuit protected ±0.05% of FSR 5 µs to 0.05% of FSR Same as input section Same as input section
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 ·
Email: sales@datel.com · Internet: www.datel.com
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PC-411/412
PC BUS INTERFACE Architecture Decodes 16 byte-wide I/O registers using address lines A9-A0. Highest base address is 3F0h. 8 bits 1 line, software selectable IRQ 3, 5, 7. Scan acquire flag (sample count). FIFO full, half full or not empty or DMA T/C. 1 Mb/sec. or greater, dependent on host PC 1 line, software-selectable, DRQ1 or DRQ3 from FIFO HF, FF, EF, or ACQ Sampling Rate per Channel The rates shown for sequential sampling are the maximum A/D converter start rates and include MUX sequencing and settling delays. For example, if four channels were scanned, the maximum sample rate on any one channel of the PC-411/412 would be 17 microseconds times 4 channels, equalling 68 microseconds (14.7 KHz per channel). Observe Nyquist sample rate rules for inputs with unknown spectral content. To avoid overload recovery delays, do not let the analog input exceed the input voltage range. Highest total system speeds will be achieved if the FIFO is block transferred using DMA or the REP INS instruction in a loop with the CX register controlling the count of samples transferred. Scan A scan would consist of a group of channels sampled together with equal delays between each A/D sample, set by the A/D star t clock. A scan is 16S or 8D channels or less. A scan uses sequential channel addressing. Frame Frames are one or more channels sampled together at each trigger with equal delays between each A/D sample, set by the A/D start clock. Each frame is started by one trigger. Either single channel or autosequential scan addressing may be used. A frame may consist of several contiguous scans with wrap around addressing. Frames are stopped when the counter 0 Acquire bit is reset to zero. PROGRAMMING (Refer to the PC-411/412 user manual for detailed programming information.) The BASE address may be selected anywhere up to 3F0h on 16-byte boundaries. At power up or PC bus reset, all registers contain zeroes except the FIFO HF and FF bits. When settling one bit in a write only register, remember to select all other bits according to the desired code. A shadow register should be considered to store the last value written. The registers may be programmed in any sequence as long as the command register is last. "x" bits are don't care or not used. I/O REGISTER MAPPING I/O Address (hex) BASE + 0 BASE + 0 BASE + 1 BASE + 1 BASE + 2 BASE + 2 BASE + 3 BASE + 3 BASE + 4 BASE + 5 BASE + 6 BASE + 7 BASE + 8 BASE + 9 BASE + 10 BASE + 11 BASE + 12 BASE + 13 BASE + 14 BASE + 15 Direction W rite Read W rite Read W rite Read W rite Read Read/Wr ite Read/Wr ite Read/Wr ite Read/Wr ite W rite W rite W rite W rite W rite W rite W rite W rite Description Command Register Status Registers Channel Address Register FIFO A/D Data Register Interrupt/DMA Register FIFO Reset Register Digital Output Port Digital Input Port Counter #0 (82C54) Counter #1 (82C54) Counter #2 (82C54) Control Word (82C54) DAC 0 low byte DAC 0 high byte DAC 1 low byte DAC 1 high byte DAC 2 low byte DAC 2 high byte DAC 3 low byte DAC 3 high byte
Data Bus Width PC Bus Interrupt (software maskable) Bus Interrupt Sources
Bus Data Transfer Rate Direct Memory Access
PARALLEL PORT Parallel Outport Parallel Inport CONNECTORS Analog Inputs, P1 25-pin female DB-25S connector on rear mounting bracket for analog inputs and trigger 9-pin female DB-25S connector on rear mounting bracket Internal header connector, 0.025 in. pins on 0.100 in. spacing, suitable for flat cable Edgeboard connector 8 lines, TTL levels, 24 mA out 8 lines, TTL levels, 2 mA in plus pullup resistor to +5V
Analog Outputs, P2 (PC-412 only) Parallel Port
PC Bus Connector, P3 MISCELLANEOUS Power Required (PC-411)
(PC-412) Operating Temp. Range Storage Temp. Range Relative Humidity Altitude Outline Dimensions
Weight Analog Section Adjustments
+5V, ±5% at 1A max. and ±12V, ±5% at 100 mA max. all supplied from the bus +5V: 2A max. ±12V: 250 mA max. 0 to +60 °C forced cooling recommended 20 to +80 °C 10% to 90%, non-condensing 0 to 10,000 feet 4.2"H x 13.31"L x 0.625"D (11,43 x 33,81 x 1,59 cm) compatible to PC bus 10 oz. (290 grams) Inputs: offset and gain Outputs: offset and gain per channel
NOTES/DEFINITIONS
Input Settling Delays The PC-411/412 will run faster in single channel operation than multichannel after the input is settled on the first channel. Total sample-to-sample throughput time must include input multiplexer settling time after changing the channel address, PGA settling time (depending on the gain), sampling A/D converter acquisition time, and A/D conversion time.
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 ·
Email: sales@datel.com · Internet: www.datel.com
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