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Part: EL2142CS
Category:
Interface and Interconnect
-> Line Drivers
-> Receiver
Description: Differential Line Receiver
Company: Elantec Semiconductor, Inc. (acquired by Intersil)
Datasheet: Download EL2142CS datasheet File size : 7 kB
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Datasheet text preview:
EL2142C
EL2142C
Differential Line Receiver
Features
Differential input range g 2 3V 150 MHz 3 dB bandwidth 400 V ms slewrate g 5V supplies or single supply 50 mA minimum output current Output swing (100X load) to within 1 5V of supplies Low power b 11 mA typical
General Description
The EL2142C is a very high bandwidth amplifier designed to extract the difference signal from noisy environments and is thus primarily targeted for applications such as receiving signals from twisted pair lines or any application where common T mode noise injection is likely to occur he EL2142C is stable for a gain of one and requires two exterT nal resistors to set the voltage gain he output common mode level is set by the reference pin (VREF) which has a b 3 dB bandwidth of over 100 MHz Generally this pin is grounded but it can be tied to any voltage T reference he output can deliver a minimum of g 50 mA and is short C cuit protected to withstand a temporary overload condition cir
Applications
Twisted pair receiver Differential line receiver VGA over twisted pair ADSL HDSL receiver Differential to single ended amplification Reception of analog signals in a O oisy environment n
onnection Diagrams
EL2142C SO P-DIP
rdering Information
E art No P
Temp Range
Package
Outline MDP0031
L2142CN b 40 C to a 85 C 8-pin DIP EL2142CS
b 40
C to a 85 C 8-pin SOIC MDP0027
2142-1
January 1996 Rev A
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these spe1ifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation c
996 Elantec Inc
EL2142C
Differential Line Receiver
Absolute Maximum Ratings (TA e 25 C)
Supply Voltage (VCC VEE) Maximum Output Current Storage Temperature Range 0V to 12 6V g 60 mA b 65 C to a 150 C Operating Junction Temperature Lead Temperature ( k5 sec) Recommended Operating Temperature
a 150 a 300 b 40 C to a 85
C C C
A Important Note ll parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA T est Level I I I I III V V D Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C T MAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only
C Electrical Characteristics
(VCC e a 5V VEE e b 5V TA e 25C VIN e 0V RL e 100 unless otherwise specified)
Parameter Vsupply IS VOS IIN ZIN CIN VDIFF AVOL VIN VOUT IOUT(min) VN VREF PSRR CMRR2 CMRR1 Description Supply Operating Range (VCC VEE) Power Supply Current (no load) Input Referred Offset Voltage Input Bias Current (VIN VINB VREF) Differential Input Resistance Differential Input Capacitance Differential Input Range Open Loop Voltage Gain Input Common Mode Voltage Range Output Voltage Swing (50X load to GND) Minimum Output Current Input Referred Voltage Noise Output Voltage Control Range Power Supply Rejection Ratio Input Common Mode Rejection Ratio (VIN e g 2V) Input Common Mode Rejection Ratio (full VIN range)
b2 5 b2 6
g2 9 g3 1 g2 0
Min
g3 0
Typ
g5 0
Max
g6 3
Test Level I I I I V V I V
Units V mA mV mA KX pF V dB V V mA nV SHz V TD is 3 3in dB dB dB
11
b 25 b 20
14 40 20
10 6 400 1
g2 3
75
a4 0
I I I V
50
60 36
a3 3
I I I I
60 60 50
70 70 60
2
EL2142C
Differential Line Receiver
AC Electrical Characteristics
(VCC e a 5V VEE e b 5V TA e 25C VIN e 0V RLOAD e 100 unless otherwise specified)
Parameter BW(b3dB) SR Tstl GBWP VREFBW(b3 dB) VREFSR dG di Description
b 3 dB Bandwidth (Gain e 1)
Min
Typ 150 400 15 200 130 100 02 02
Max
Test Level V V V V V V V V
Units MHz V ms ns MHz MHz TD is 1 8in V msec %
Slewrate Settling time to 1% Gain bandwidth product VREF b3dB Bandwidth VREF Slewrate Differential gain at 3 58 MHz Differential phase at 3 58 MHz
Pin Description
Pin Number 1 2 3 4 5 6 7 8 Pin Name VFB VIN VINB VREF NC VCC VEE VOUT Positive supply voltage Negative supply voltage Output voltage Feedback input Non-inverting input Inverting input Sets output voltage level to VREF when VIN e VINB Function
3
EL2142C
Differential Line Receiver
Typical Performance Curves
IS vs Supply Voltage Frequency Response (Gain e 1)
2142 2
2142 3
Frequency Response vs Resistor R1 (Gain e 4)
CMRR vs Frequency
2142 4
2142 5
VREF Frequency Response
Distortion vs Frequency (GAIN e 3 RLOAD e 100X) VIN e 2V pk pk
2142 6
2142 7
4
EL2142C
Differential Line Receiver
Applications Information
2142-8
Gain Equation
VOUT e ((R2 a R1) R1) c (VIN-VINB a VREF) when R1 tied to GND VOUT e ((R2 a R1) R1) c (VIN-VINB) when R1 tied to VREF
Choice of Feedback Resistor
For a gain of one VOUT may be shorted back to VFB but 100X 200X improves the bandwidth F or gains greater than one there is little to be gained from choosing resistor R1 value below 200X for it would only result in increased power dissipation and potential signal distortion Above 200X the bandwidth response will develop some peaking (for a gain of one) but substantially higher R1 values may be used for higher voltage gains such as up to 1 kX at a gain of four before peaking will develop
apacitance Considerations
As with many high bandwidth amplifiers the EL2142C prefers not to drive highly capacitive loads It is best if the capacitance on VOUT is kept below 10 pF if the user does not want gain peaking to develop The VFB node forms a potential pole in the feedback loop so capacitance should be minimized on this node for maximum T bandwidth he amount of capacitance tolerated on any of C ese nodes in an actual application will also be th dependent on the gain setting and the resistor 5 values in the feedback network
Others parts begin by el
EL-1 EL-2 EL-3 EL-4 EL-5 EL-6 EL-7 EL-8 EL-9 EL-10 EL-11 EL-12 EL-13 EL-14 EL-15 EL-16 EL-17 EL-18
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