Details, datasheet, quote on part number: MC9S08SL16CTJ
PartMC9S08SL16CTJ
CategorySemiconductors => Integrated Circuits (ICs) => MCU, MPU, DSP, DSC, SoC Processors => Microcontrollers (MCU)
TitleMicrocontrollers (MCU) 9S08 UC W/ 16K 0.25UM SG
DescriptionThe Freescale Semiconductor MC9S08EL 8 - bit microcontroller ( MCU ) with embedded Slave LIN Interface Controller (SLIC) and EEPROM increase LIN slave performance and reduce development time. This Freescale Semiconductor 8 - bit MCU family supports high performance LIN 2.x and SAE J2602 protocols and enables high performance with the fewest interrupts on CPU of any known solution. The MC9S08EL MCU includes integrated ADC for fast and easy conversion of analog inputs with 2.5µs conversion time and provides high system protection with Watchdog Computer Operating Properly (COP), low-voltage detection, illegal status detection, and flash block protection.
CompanyFreescale Semiconductor
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Specifications 
ManufacturerFreescale Semiconductor
Product CategoryMicrocontrollers (MCU)
RoHS Details
CoreHCS08
Processor SeriesS08SL
Data Bus Width8 bit
Maximum Clock Frequency200 KHz
Program Memory Size16 KB
Data RAM Size512 B
On-Chip ADCYes
Operating Supply Voltage5.5 V
Package / CaseTSSOP-20
Mounting StyleSMD/SMT
A/D Bit Size10 bit
A/D Channels Available12
Height1.05 mm
Interface TypeI2C, SCI, SLIC, SPI
Length6.6 mm
Maximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 C
Number of Programmable I/Os16
Number of Timers2
PackagingTube
Program Memory TypeFlash
Supply Voltage (Max)5.5 V
Supply Voltage (Min)2.7 V
Width4.5 mm
MC9S08SL16CTJ photo

 

Features, Applications

40-MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Support for to 32 interrupt/reset sources

ADC 16-channel, 10-bit resolution, 2.5 s conversion time, automatic compare function, temperature sensor, internal bandgap reference channel; runs in stop3 ACMPx Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can optionally be routed to TPM module; runs in stop3 SCI Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake-up on active edge SLIC Supports LIN 2.0 and SAE J2602 protocols; to 120 kbps, full LIN message buffering, automatic bit rate and frame synchronization, checksum generation and verification, UART-like byte transfer mode SPI Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting IIC to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer TPMx One 4-channel (TPM1) and one 2-channel (TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel RTC 8-bit modulus real-time counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar, or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components

FLASH read/program/erase over full operating voltage and temperature EEPROM in-circuit programmable memory; program and erase while executing FLASH; erase abort Random-access memory (RAM) Security circuitry to prevent unauthorized access to RAM and NVM contents

Two very low-power stop modes Reduced power wait mode Very low-power real-time interrupt for use in run, wait, and stop

Oscillator (XOSC) Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz Internal clock source (ICS) Contains a frequency-locked loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 220 MHz

Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt; selectable trip points Illegal opcode detection with reset Illegal address detection with reset FLASH and EEPROM block protect

22 general purpose I/O pins 16 interrupt pins with selectable polarity Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins.

Single-wire background debug interface Breakpoint capability allows single breakpoint setting during in-circuit debugging (plus two more breakpoints in the on-chip debug module) In-circuit emulation (ICE) debug module contains two comparators and nine trigger modes; eight-deep FIFO for storing change-of-flow address and event-only data; supports both tag and force breakpoints


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