|Category||Semiconductors => Integrated Circuits (ICs) => MCU, MPU, DSP, DSC, SoC Processors => Microcontrollers (MCU)|
|Title||Microcontrollers (MCU) 128k Flash Non-analog IP|
|Datasheet||Download MCF51JE128CLK datasheet
|Data Bus Width||32 bit|
|Maximum Clock Frequency||50 MHz|
|Program Memory Size||128 KB|
|Data RAM Size||32 KB|
|Operating Supply Voltage||1.8 V to 3.6 V|
|Package / Case||LQFP-80|
|Interface Type||I2C, SCI, SPI, USB|
|Maximum Operating Temperature||+ 85 C|
|Minimum Operating Temperature||- 40 C|
|Number of Programmable I/Os||47|
|Number of Timers||2|
|Program Memory Type||Flash|
|Freescale Semiconductor Data Sheet: Advanced Information
The MCF51JE256 series devices are members of the low-cost, low-power, high-performance ColdFire® V1 family of 32-bit microcontrollers (MCUs). Not all features are available in all devices or packages; see Table 2 for a comparison of features by device.
32-Bit ColdFire V1 Central Processor Unit (CPU) to 50.33-MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V and 20 MHz CPU above 1.8 V across temperature range to 105°C. ColdFire Instruction Set Revision C (ISA_C). 32-bit multiply and accumulate (MAC) supports signed or unsigned integer or signed fractional inputs. On-Chip Memory 256 K Flash comprised of two independent 128 K flash arrays; read/program/erase over full operating voltage and temperature; allows interrupt processing while programming. 32 Kbytes System Random-access memory (RAM). Security circuitry to prevent unauthorized access to RAM and Flash contents. Power-Saving Modes Two ultra-low power stop modes. Peripheral clock enable register can disable clocks to unused modules to reduce currents. Time of Day (TOD) Ultra low-power 1/4 sec counter with to 64s timeout. Ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the TOD. 6 usec typical wake up time from stop3 mode. Clock Source Options Oscillator (XOSC1) Loop-control Pierce oscillator; 32.768 kHz crystal or ceramic resonator dedicated for TOD operation. Oscillator (XOSC2) for high frequency crystal input for MCG reference to be used for system clock and USB operations. Multipurpose Clock Generator (MCG) PLL and FLL; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 4 kHz to 50 MHz. System Protection Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock. Low-voltage detection with reset or interrupt; selectable trip points; separate low voltage warning with optional interrupt; selectable trip points. Illegal opcode and illegal address detection with reset. Flash block protection for each array to prevent accidental write/erasure. Hardware CRC to support fast cyclic redundancy checks. Development Support Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM connection supports same electrical interface used by the S08 family debug modules. Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 data). On-chip trace buffer provides programmable start/stop recording conditions. Peripherals USB Dual-role USB On-The-Go (OTG) device, supports USB in either device, host or OTG configuration. On-chip transceiver and 3.3V regulator
help save system cost, fully compliant with USB Specification 2.0. Allows control, bulk, interrupt and isochronous transfers. SCIx Two serial communications interfaces with optional 13-bit break; option to connect Rx input to PRACMP output on SCI1 and SCI2; High current drive on SCI1 and SCI2; wake-up from on Rx edge. SPI1 Serial peripheral interface with 64-bit FIFO buffer; or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting. SPI2 Serial peripheral interface with full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting. IIC to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing. CMT Carrier Modulator timer for remote control communications. Carrier generator, modulator and driver for dedicated infrared out (IRO). Can be used as an output compare timer. TPMx Two 4-channel Timer/PWM Module; Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; external clock input/pulse accumulator. Mini-FlexBus Multi-function external bus interface with user programmable chip selects and the option to multiplex address and data lines. PRACMP Analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation ADC12 12-bit Successive approximation ADC with 4 differnential channels and up to12 single-ended channels; internal bandgap reference channel; operation in stop3; fully functional from to 1.8V. PDB Programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided 1 to bus divided 2048; 8 trigger outputs for ADC module provides periodic coordination of ADC sampling sequence with sequence completion interrupt; Back-to-Back mode and Timed mode. DAC 12-bit resolution; 16-word data buffers with configurable watermark. Input/Output to 68 GPIOs and 1 output-only pin. Voltage Reference output (VREFO). Dedicated infrared output pinwith high current sink capability. to 16 KBI pins with selectable polarity. to 16 pins of rapid general purpose I/O.
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
80-Pin LQFP.10 Pin Assignments.11 Parameter Classification.15 Absolute Maximum Ratings.16 Thermal Characteristics.17 ESD Protection DC Characteristics.19 Supply Current Characteristics.23 PRACMP Electricals.26 12-bit DAC Electricals.27 ADC Characteristics.29 MCG and External Oscillator (XOSC) Characteristics.33 Mini-FlexBus Timing Characteristics.37 3.12.1 Control Timing.37 3.12.2 TPM Timing.39 SPI Characteristics.40 Flash Specifications.44 USB Electricals.45 VREF Electrical Specifications.46 Part Numbers.48 Package Information.48 Mechanical Drawings.49 Figure 14.Timer Input Capture Pulse. Figure 15.SPI Master Timing (CPHA = 0). Figure 16.SPI Master Timing (CPHA = 1). Figure 17.SPI Slave Timing (CPHA = 0). Figure 18.SPI Slave Timing (CPHA = 1). Figure 19.Typical Output vs. Temperature. Figure 20.Typical Output vs. VDD.
Table 1. MCF51JE256/128 Features by MCU and Package. 4 Table 2. MCF51JE256/128 Functional Units. 5 Table 3. Package Pin Assignments. 11 Table 4. Parameter Classifications. 15 Table 5. Absolute Maximum Ratings. 16 Table 6. Thermal Characteristics. 17 Table 7. ESD and Latch-up Test Conditions. 18 Table 8. ESD and Latch-Up Protection Characteristics. 18 Table 9. DC Characteristics. 19 Table 10.Supply Current Characteristics. 23 Table 11.Typical Stop Mode Adders. 25 Table 12.PRACMP Electrical Specifications. 26 Table 13.DAC 12LV Operating Requirements. 27 Table 14.DAC 12-Bit Operating Behaviors. 28 Table 15.12-bit ADC Operating Conditions. 29 Table 16.12-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD 8 MHz) 31 Table 17.MCG (Temperature Range to 105°C Ambient). 33 Table 18.XOSC (Temperature Range to 105°C Ambient) 34 Table 19.Mini-FlexBus AC Timing Specifications. 35 Table 20.Control Timing. 37 Table 21.TPM Input Timing. 39 Table 22.SPI Timing. 40 Table 23.SPI Electrical Characteristic. 41 Table 24.Flash Characteristics. 44 Table 25.Internal USB 3.3 V Voltage Regulator Characteristics 45 Table 26.VREF Electrical Specifications. 46 Table 27.VREF Limited Range Operating Requirements. 46 Table 28.VREF Limited Range Operating Behaviors. 46 Table 29.Orderable Part Number Summary. 48 Table 30.Package Descriptions. 48 Table 31.Revision History. 49
Figure 1. MCF51JE256/128 Block Diagram. 3 Figure 2. 104-Pin MAPBGA. 7 Figure 3. 100-Pin LQFP. 8 Figure 4. 81-Pin MAPBGA. 9 Figure 5. 80-Pin LQFP. 10 Figure 6. Stop IDD versus Temperature. 26 Figure 7. Offset at Half Scale vs Temperature. 28 Figure 8. ADC Input Impedance Equivalency Diagram. 30 Figure 9. Mini-FlexBus Read Timing. 36 Figure 10.Mini-FlexBus Write Timing. 36 Figure 11.Reset Timing. 38 Figure 12.IRQ/KBIPx Timing. 38 Figure 13.Timer External Clock. 39
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