The 32-bit MPC5746M Qorivva MCU is built on Power Architecture® technology and is our a multicore safety architecture to assist customers in ISO26262 functional safety certification for ASIL-D safety integrity. In order to minimize additional software and module-level features to reach this target, on-chip redundancy is offered for the critical components of the MCU. These include multiple CPU computational cores with delayed lockstep, I/O processor core, DMA controller, interrupt controller, dual crossbar bus system, memory protection unit, fault collection unit (FCCU), flash memory and RAM controllers, peripheral bus bridge, system and watchdog timers and end-to-end error correction coding (ECC).
· Engine control· Gasoline direct injection· Common rail diesel injection or clean diesel· Hybrid electric and full electric vehicle (HEV/EV) motor control· Cylinder or multi-valve deactivation· Transmission control
first powertrain device with more than two processing cores. The MPC5746M addresses the requirements of direct injection, advanced diesel, transmission, hybrid electric and full electric powertrain applications to meet the most extreme regulatory and environmental emission qualifications. The MPC5746M is part of the SafeAssure program, designed to help system manufacturers more easily achieve compliance with functional safety standards. The SafeAssure program is built around
Computational Shell 200 MHz Cores 200 MHz Crossbar Power® e200Z4 FPU VLE 8 KB I-Cache 4 KB D-Cache Core MPU I-RAM 16 KB D-RAM 64 KB SWT STM INTC
Peripheral Control Shell Debug JTAG Nexus 3+ DigRF Aurora Power Control T Sensor PMU I-Fetch 200 MHz Core 100 MHz Crossbar: 50 MHz Periphery SWT FlexRayTM Power e200Z4 STM SIPI/DigRF DSP INTC Ethernet FPU eDMA VLE Hardware I-RAM 8 KB I-Cache Security Module D-RAM 64 KB Core MPU Power in LS Power e200Z4 FPU VLE 8 KB I-Cache 4 KB D-Cache Core MPU I-RAM 16 KB D-RAM 64 KB SWT STM INTC
High-Bandwidth Cross Bar Switch with ECC: 200 MHz System Memory Protection Unit AMU Flash Control SRAM Control
Platform Cross Bar Switch with ECC: 100 MHz System Memory Protection Unit Bridge A Bridge B
A comprehensive suite of hardware and software development tools is available to help simplify and speed system design. Development support is available from worldclass tool vendors, providing compilers, debuggers and simulation development environments.
Two independent e200z4 computational cores operating to 200 MHz Single e200z4 I/O core operating to 200 MHz· On-chip DSP and floating point unit 4 MB flash memory with error correction coding KB of total SRAM with ECC (128 KB system and 192 KB data) with tightly coupled SRAM to 64-channel enhanced direct memory access (eDMA) control Functional safety support· Single 200 MHz e200z4 core for delayed lockstep· End-to-end ECC· Memory and logic built-in self test· Fault collection and correction unit 120-channel general timer module (GTM103)
Significant performance allows users to enable virtual sensors and eliminate many external ICs. The capability to reduce code footprint to 30 percent for improved code density and reduced memory requirements. Generous memory supports autocode generation and modeling tools that speed time to market. High RAM size to meet next-generation requirements. Tightly coupled RAM increases data transfer speed eDMA channels to manage on-chip memory needs. Helps simplify compliance for automotive safety systems targeting ISO 26262 and ASIL-D.
Compilers· Green Hills Software· Wind River Diab· HiTech Debuggers· P&E Micro· Lauterbach· Green Hills Software· PLS Runtime Software· Flash and EEPROM drivers· Software core self test· AUTOSAR MCAL 4.0 Operating Systems and Calibration Tools· AUTOSAR OS 4.0 provided by thirdparty vendors· ETAS
New complex timer based on Bosch licensed specification is optimized for engine control systems. Using these complex timers results in precise fuel and air delivery and improved gas mileage. Allows independent and simultaneous conversions of analog signals and helps to filter unwanted noise to optimize combustion. Capable to 10 Mbps bandwidth. Capable to 100 Mbps bandwidth. High-speed CAN communication with time triggered support. Supports LIN/J2602, microsecond bus, sensor interface communication and high-speed parallel communication. On-chip security for code protection. High-speed debug capability. Offers significant I/O and functionality.
to 60-channel analog-to-digital converters (ADC) including 6 x ADC converters Dual-channel FlexRayTM controller Ethernet controller (FEC) 3x M-CAN TT-CAN 5x LINFlex 7x dSPI and 3x PSI-5 and 10 x SENT DigRF SIPI support Hardware security module Aurora debug and trace support 176-pin LQFP package (with exposed pad) 292-pin PBGA package
Functional Safety. Simplified. Our SafeAssure functional safety program is designed to help system manufacturers more easily achieve system compliance with International Standards Organization (ISO) 26262 and 61508 functional safety standards. The program highlights Freescale solutions--hardware and software--that are optimally designed to support functional safety implementations and come with a rich set of enablement collateral. For more information, visit freescale.com/SafeAssure.
EVB Motherboard EVB Daughter Card EVB Daughter Card EVB Daughter Card
N/A (to be used with adapter) 176 LQFP with socket adapter 216 Fusion Quad (no socket) 292 BGA with socket adapter
PPC5746MQK0MKU5R (production) PPC5746MQK0MOU5R (calibration only) PPC5746MQK0MMP5R (production) PPC5746M2K0MMP5R (calibration only)
Freescale, the Freescale logo and Qorivva are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SafeAssure and the SafeAssure logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Document Number: MPC5746MFS REV 0