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Part: EDL5132CBMA
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 512 Mb
Description: 512 Megabit Mobile RAM Devices
Company: Elpida Memory
Datasheet: Download EDL5132CBMA datasheet File size : 612 kB
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Datasheet text preview:
PRELIMINARY DATA SHEET
512M bits Mobile RAM MCP 2 pcs of 256Mb components
EDL5132CBMA (16M words × 32 bits)
Description
The EDL5132CBMA is a 512M bits Mobile RAM MCP (Multi Chip Package) organized as 4,194,304 words × 32 bits × 4 banks, 2 pieces of 256M bits Mobile RAM in one package. It is packaged in 90-ball FBGA.
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
1 2 3 4 5 6 7 8 9
A
Features
· Low voltage power supply VDD: 1.7V to 1.95V VDDQ: 1.7V to 1.95V · Wide temperature range (-25°C to 85°C) · Programmable Partial Array Self Refresh · Programmable Driver Strength · Auto Temperature Compensated Self Refresh by built-in temperature sensor. · Deep power down mode · Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge · Pulsed interface · Possible to assert random column address in every cycle · Quad internal banks controlled by BA0 and BA1 · Byte control by DQM · Wrap sequence = Sequential/ Interleave · /CAS latency (CL) = 2, 3 · Automatic precharge and controlled precharge · Auto refresh and self refresh · ×32 organization · 8,192 refresh cycles/64ms · Burst termination by Burst stop command and Precharge command · FBGA package with lead free solder (Sn-Ag-Cu)
B C
DQ26 DQ24 VSS DQ28 VDDQ VSSQ VSSQ DQ27 DQ25
VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC A3 A6 A12 A9 NC VSS
F
VSS DQM3
G
A4 A5 A8 CKE NC
H
A7
J
CLK
K
DQM1 /WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
L
VDDQ DQ8
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 VDD DQ0 DQ2
R
DQ13 DQ15 VSS
(Top view) A0 to A12 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power supply Ground Power supply for DQ Ground for DQ No connection
Document No. E0490E20 (Ver. 2.0) Date Published July 2004 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004
EDL5132CBMA
Ordering Information
Part number EDL5132CBMA-10-E Organization (words × bits) 16M × 32 Internal banks 4 Clock frequency MHz (max.) 100 /CAS latency 3 Package 90-ball FBGA
Part Number
E D L 51 32 C B MA - 10 - E
Elpida Memory
Type D: Monolithic Device
Product Code L: Mobile RAM
Environment Code E: Lead Free Speed 10: 100MHz/CL3 Package MA: Stacked FBGA Die Rev.
Density / Bank 51: 512M /4-bank Bit Organization 32: x32 Voltage, Interface C: VDD = 1.8V, VDDQ = 1.8V, LVCMOS
Preliminary Data Sheet E0490E20 (Ver. 2.0)
2
EDL5132CBMA
CONTENTS Description...........1 Features......1 Pin Configurations ........ 1 Ordering Information.....2 Part Number ........ 2 Electrical Specifications......4 Block Diagram ............10 Pin Function.......11 Command Operation ..13 Truth Table ........17 Simplified State Diagram ...........23 Initialization ........24 Programming Mode Registers............24 Address Bits of Bank-Select and Precharge .....28 Operation of the Mobile RAM ....29 Timing Waveforms......37 Package Drawing .......59 Recommended Soldering Conditions..........60
Preliminary Data Sheet E0490E20 (Ver. 2.0)
3
EDL5132CBMA
Electrical Specifications
· All voltages are referenced to VSS (GND). · After power up, wait more than 200 µs and then, execute Power on sequence and two Auto Refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating 0.5 to +2.6 0.5 to +2.6 50 1.0 25 to +85 55 to +125 Unit V V mA W °C °C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 25 to +85°C)
Parameter Supply voltage DQ Supply voltage Input high voltage Input low voltage Symbol VDD VSS, VSSQ VDDQ VIH VIL min. 1.7 0 1.7 0.8 × VDDQ 0.3 typ. 1.8 0 1.8 max. 1.95 0 1.95 VDDQ + 0.3 0.3 Unit V V V V V 1 2 Notes
Notes: 1. VIH (max.) = 2.6V (pulse width 5ns) 2. VIL (min.) = 1.0V (pulse width 5ns)
Preliminary Data Sheet E0490E20 (Ver. 2.0)
4
EDL5132CBMA
DC Characteristics 1 (TA = 25 to +85°C, VDD = VDDQ = 1.7V to 1.95V, VSS, VSSQ = 0V)
Parameter /CAS latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current (CL = 2) (CL = 3) Refresh current (CL = 2) (CL = 3) Standby current in deep power down mode Symbol IDD1 IDD1 IDD2P IDD2PS Grade max. 80 80 1.2 1 Unit mA mA mA mA Test condition Burst length = 1 tRC tRC min., IO = 0mA, One bank active CKE VIL max., tCK = 15ns CKE VIL max., tCK = CKE VIH min., tCK = 15ns, /CS VIH min., Input signals are changed one time during 30ns. CKE VIH min., tCK = , Input signals are stable. CKE VIL max., tCK = 15ns CKE VIL max., tCK = CKE VIH min., tCK = 15 ns, /CS VIH min., Input signals are changed one time during 30ns. CKE VIH min., tCK = , Input signals are stable. tCK tCK min., IOUT = 0mA, All banks active Notes 1
IDD2N
6
mA
IDD2NS IDD3P IDD3PS
4 2 1.6
mA mA mA
IDD3N
30
mA
IDD3NS IDD4 IDD4 IDD5 IDD5 IDD7
10 90 120 110 110 20
mA mA mA mA mA µA
2
tRC tRC min.
3
CKE 0.2V
Self refresh current PASR="000" (Full) PASR="001" (2BK) PASR="010" (1BK) PASR="000" (Full) PASR="001" (2BK) PASR="010" (1BK)
Symbol IDD6
Grade
typ. 400 360 300
max. 800 600 500
Unit µA µA µA µA µA µA
Condition TA 85°C +0°C/-15°C, CKE 0.2V
Notes 4
IDD6
TA 45°C, CKE 0.2V
4
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured on condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured on condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). 4. IDD6 is specified when self refresh state is maintained long enough under the specified TA condition, after a busy sequence of read and write operations.
Preliminary Data Sheet E0490E20 (Ver. 2.0)
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Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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