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Part: EDR2518ABSE-AD
Category:
Memory
-> DRAM
-> RDRAM
Description:
Company: Elpida Memory
Datasheet: Download EDR2518ABSE-AD datasheet File size : 173 kB
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Datasheet text preview:
PRELIMINARY DATA SHEET
288M bits Direct Rambus DRAM
EDR2518ABSE (512K words × 18 bits × 32s banks)
Description
The EDR2518AB (Direct RDRAM) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The EDR2518AB is 1066MHz 288Mbits Direct Rambus DRAM (RDRAM), organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 800MHz to 1066MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 0.9375ns per two bytes (7.5ns per sixteen bytes). The architecture of the Direct RDRAM devices allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM devices 32 banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking. It is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAM devices operate from a 2.5V supply.
Features
· Highest sustained bandwidth per DRAM device -- 2.1 GB/s sustained data transfer rate -- Separate control and data buses for maximized efficiency -- Separate row and column control buses for easy scheduling and highest performance -- 32 banks: four transactions can take place simultaneously at full bandwidth data rates · Low latency features -- Write buffer to reduce read latency -- 3 precharge mechanisms for controller flexibility -- Interleaved transactions · Advanced power management: -- Multiple low power states allows flexibility in power consumption versus time to active state -- Power-down self-refresh · Organization: 2K bytes pages and 32 banks, x 18 · Uses Rambus Signaling Level (RSL) for up to 1066MHz operation · FBGA (µ BGA) package is Sn-Pb or lead free solder (Sn-Ag-Cu)
Document No. E0260E40 (Ver. 4.0) Date Published April 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002-2003
EDR2518ABSE
Ordering Information
Part number EDR2518ABSE-AEP EDR2518ABSE-AE EDR2518ABSE-AD EDR2518ABSE-8C EDR2518ABSE-AEP-E EDR2518ABSE-AE-E EDR2518ABSE-AD-E EDR2518ABSE-8C-E Organization* words × bits × Internal Banks 512K x 18 x 32s Clock frequency MHz (max.) 1066 1066 1066 800 1066 1066 1066 800 /RAS access time (ns) 32 (-32P) 32 (-32) 35 40 32 (-32P) 32 (-32) 35 40 Package 80-ball FBGA (µBGA)
Note: The "32s" designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture
Part Number
E D R 25 18 A B SE - AEP - E
Elpida Memory Type D: Monolithic Device Product Code R: RDRAM Density & Bit Organization 2518: 288M (x18 bit) Environment Code Blank: Sn-Pb Solder E: Lead Free Speed AEP: 1066MHz (tRAC= 32ns, tDAC= 3clocks) AE: 1066MHz (tRAC= 32ns) AD: 1066MHz (tRAC= 35ns) 8C: 800MHz (tRAC= 40ns)
Package SE: FBGA (µBGA with back cover)
Voltage, Interface A: 2.5V, RSL Die Rev.
2
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Pin Configuration
80-ball FBGA (µ BGA) µ Top View
10 9 8 7 6 5 4 3 2 1
O O O O O
O O O O O O O O O O O O O O O O O O O O O O O O O O O
O O O
O O O O O
O O
O O O B
O O O C
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O O S
O O O T
O O
A
D
E
F
G
H
J
K
L
M
N
P
R
U
10 9 8 7 6 5 4 3 2 1 A
GND GND
VDD
GND
GND
VDD
VDD
DQA8
CMD DQA7
VDD
DQA5
GND DQA3
GNDa DQA1
GNDa CTMN
VDD
CTM
VDD
GND
GND COL3
VDD
COL1
VDD
DQB1
GND DQB3
GND DQB5
VCMOS DQB7
VDD
DQB8
GND
VDD
ROW2 ROW0
VDD
GND GND
DQA6 SCK
DQA4
DQA2
DQA0
CFM GND
CFMN
ROW1 VREF
COL4 GND
COL2
COL0 GND
DQB0 GND
DQB2
DQB4 SIO0
DQB6 SIO1
GND GND
GND
VDD
VCMOS GND
VDD
VDDa
VDD
VDD
VDD
VDD
GND
GND
VDD
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Preliminary Data Sheet E0260E40 (Ver. 4.0)
3
EDR2518ABSE
Pin Description
Signal SIO0, SIO1 Input / Output Type
Note1
#pins 2
Description Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management.
Input / Output CMOS
CMD
Input
CMOS Note1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management.
SCK
Input
CMOS
Note1
1
Serial clock input. Clock source used for reading from and writing to the control registers.
VDD VDDa VCMOS GND GNDa DQA8..DQA0 Input / Output RSL
Note2
18 1 2 22 2 9
Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM.
CFM
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity.
CFMN
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity.
VREF CTMN Input RSL
Note2
1 1
Logic threshold reference voltage for RSL signals. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity.
CTM
Input
RSL Note2
1
Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity.
ROW2..ROW0
Input
RSL Note2
3
Row access control. Three pins containing control and address information for row accesses.
COL4..COL0
Input
RSL
Note2
5
Column access control. Five pins containing control and address information for column accesses.
DQB8..DQB0
Input / Output
RSL
Note2
9
Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM.
Total pin count per package
80
Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero. 2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
4
Preliminary Data Sheet E0260E40 (Ver. 4.0)
EDR2518ABSE
Block Diagram
RQ7..RQ5 or ROW2..ROW0
3 RCLK
DQB8..DQB0
9
CTM CTMN SCK, CMD SIO0, SIO1
2 2
CFM CFMN
RQ4..RQ0 or COL4..COL0
5
DQA8..DQA0
9 RCLK
1:8 Demux
TCLK RCLK
1:8 Demux
Packet Decode ROWR ROWA
11 ROP AV 5 DR 5 BR 9 R
Control Registers COLX
6 5 5
Packet Decode COLC
5 5 5 7
COLM
8 8
REFR
Power Modes
DEVID
XOP M
DX
BX
COP S
DC
BC
C
MB
MA
Match DM
Mux Row Decode PRER ACT
Match XOP Decode PREX
Match
Write Buffer Mux Mux
Column Decode & Mask Sense Amp 64x72
DRAM Core
64x72
SAmp SAmp 0/1 0
PREC 512x128x144 64x72
SAmp SAmp 0/1 0
RD, WR
72
Internal DQB Data Path
72
Bank 0 Bank 1 Bank 2
Internal DQA Data Path
72
72
SAmp 1/2
SAmp 1/2
RCLK
9
9
· · ·
SAmp 13/14
· · ·
Bank 13 Bank 14 Bank 15
· · ·
SAmp 13/14
9
9
RCLK
Write Buffer
Write Buffer
1:8 Demux
1:8 Demux
SAmp 14/15
9
9
SAmp 14/15
SAmp 15
SAmp 15
SAmp 16
SAmp 16
SAmp 16/17
Bank 16 Bank 17 Bank 18
SAmp 16/17
TCLK
9
9
TCLK
SAmp 17/18
SAmp 17/18
9
8:1 Mux
· · ·
SAmp 29/30
· · ·
Bank 29 Bank 30 Bank 31
· · ·
SAmp 29/30 SAmp SAmp 30/31 31
8:1 Mux
9
SAmp SAmp 30/31 31
Preliminary Data Sheet E0260E40 (Ver. 4.0)
5
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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