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Part: EDS1232AASE-60L-E
Category:
Memory
-> DRAM
-> SDR SDRAM
Description:
Company: Elpida Memory
Datasheet: Download EDS1232AASE-60L-E datasheet File size : 719 kB
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DATA SHEET
128M bits SDRAM
EDS1232AASE (4M words × 32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA (µBGA).
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA (µBGA)
1 2 3 4 5 6 7 8 9
A
DQ26 DQ24 VSS VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 /CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 /CS A1 A11 /RAS
Features
· · · · · 3.3V power supply Clock frequency: 166MHz (max.) Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently · Burst read/write operation and burst read/single write operation capability · Programmable burst length (BL): 1, 2, 4, 8 and full page · 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) · Programmable /CAS latency (CL): 2, 3 · Byte control by DQM · Refresh cycles: 4096 refresh cycles/64ms · 2 variations of refresh Auto refresh Self refresh · FBGA(µBGA) package is lead free solder (Sn-Ag-Cu)
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC A3 A6 NC A9 NC VSS
F
VSS DQM3
G
A4 A5 A8 CKE NC
H
A7
J
CLK
K
DQM1 /WE DQM0 DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
L
VDDQ DQ8
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 VDD DQ0 DQ2
R
DQ13 DQ15 VSS
(Top view) A0 to A11 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection
Document No. E0350E10 (Ver. 1.0) Date Published February 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003
EDS1232AASE
Ordering Information
Part number EDS1232AASE-60-E EDS1232AASE-75-E EDS1232AASE-60L-E EDS1232AASE-75L-E Supply voltage 3.3V Organization (words × bits) Internal Banks 4M × 32 4 Clock frequency MHz (max.) 166 133 133 100 166 133 133 100 /CAS latency 3 2 3 2 3 2 3 2 Package 90-ball FBGA (µBGA)
Part Number
E D S 12 32 A A SE - 60 L - E
Elpida Memory Type
D: Monolithic Device
Environment Code Blank: Sn-Pb Solder E: Lead Free Spec. Detail Blank: Normal L: Low Power Speed 60: 166MHz/CL3 133MHz/CL2 75: 133MHz/CL3 100MHz/CL2 Package SE: FBGA (µBGA with back cover)
Product Code S: SDRAM Density / Bank 12: 128M/4-Bank Bit Organization 32: x32 Voltage, Interface A: 3.3V, LVTTL Die Rev.
Data Sheet E0350E10 (Ver. 1.0)
2
EDS1232AASE
CONTENTS Description .......... 1 Features .............. 1 Pin Configurations ........ 1 Ordering Information .... 2 Part Number ........ 2 Electrical Specifications...... 4 Block Diagram ..... 9 Pin Function ...... 10 Command Operation .. 11 Truth Table ........ 15 Simplified State Diagram........... 21 Programming Mode Registers ........... 22 Mode Register ............ 23 Power-up sequence ... 26 Operation of the SDRAM .......... 27 Timing Waveforms ..... 43 Package Drawing ....... 50 Recommended Soldering Conditions.......... 51
Data Sheet E0350E10 (Ver. 1.0)
3
EDS1232AASE
Electrical Specifications
· All voltages are referenced to VSS (GND). · After power up, execute power up sequence and initialization sequence before proper device operation is achieved (refer to the Power up sequence). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating 0.5 to +4.6 0.5 to +4.6 50 1.0 0 to +70 55 to +125 Unit V V mA W °C °C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70°C) °
Parameter Supply voltage Symbol VDD, VDDQ VSS Input high voltage Input low voltage VIH VIL min. 3.0 0 2.0 0.3*2 typ. 3.3 0 max. 3.6 0 VDD + 0.3* 0.8
1
Unit V V V V
Notes
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width 5ns). 2. VIL (min.) = 1.5V (pulse width 5ns).
Data Sheet E0350E10 (Ver. 1.0)
4
EDS1232AASE
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V±0.3V, VSS, VSSQ = 0V) ° ±
Parameter /CAS latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current Refresh current Self refresh current Self refresh current (L-version) Symbol IDD1 IDD1 IDD2P IDD2PS Grade -60 -75 -60 -75 max. 120 105 120 105 1 1 Unit mA mA mA mA Test condition Burst length = 1 tRC tRC (min.) IO = 0mA One bank active CKE VIL (max.) tCK = 15ns CKE VIL (max.) tCK = CKE VIH (min.) tCK = 15ns CS VIH (min.) Input signals are changed one time during 30ns CKE VIH (min.) tCK = CKE VIL (max.) tCK = 15ns CKE VIL (max.), tCK = CKE VIH (min.), tCK = 15 ns, /CS VIH (min.), Input signals are changed one time during 30ns. CKE VIH (min.), tCK = , tCK tCK (min.), IO = 0mA, All banks active tRC tRC (min.) VIH VDD - 0.2V, VIL GND + 0.2V 2 3 Notes 1
IDD2N
20
mA
IDD2NS IDD3P IDD3PS
8 5 4
mA mA mA
IDD3N
25
mA
IDD3NS IDD4 IDD5 IDD6 IDD6 -xxL -60 -75 -60 -75
15 200 180 240 210 2.0 0.6
mA mA mA mA mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V±0.3V, VSS, VSSQ = 0V) ° ±
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. 1.0 1.5 2.4 -- max. 1.0 1.5 -- 0.4 Unit µA µA V V Test condition 0 = VIN = VDDQ, VDDQ = VDD, All other pins not under test = 0V 0 = VIN = VDDQ DOUT is disabled IOH = 2 mA IOL = 2 mA Notes
Data Sheet E0350E10 (Ver. 1.0)
5
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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