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Part: EDS1232AATA-60
Category:
Memory
-> DRAM
-> SDR SDRAM
Description: 128M; Mobile RAM
Company: Elpida Memory
Datasheet: Download EDS1232AATA-60 datasheet File size : 719 kB
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DATA SHEET
128M bits SDRAM
EDS1232AATA (4M words × 32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 86-pin plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
86-pin Plastic TSOP(II) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS A11 BA0 BA1 A10(AP) A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (Top view) 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
Features
· · · · · 3.3V power supply Clock frequency: 166MHz (max.) Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently · Burst read/write operation and burst read/single write operation capability · Programmable burst length (BL): 1, 2, 4, 8 and full page · 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) · Programmable /CAS latency (CL): 2, 3 · Byte control by DQM · Refresh cycles: 4096 refresh cycles/64ms · 2 variations of refresh Auto refresh Self refresh
A0 to A11, BA0, BA1
Address inputs Bank select DQ0 to DQ31 Data input/output /CS Chip select /RAS Row address strobe Column address strobe /CAS Write enable /WE
DQM0 to DQM3 DQ mask enable
CKE CLK VDD VSS
VDDQ VSSQ
Clock enable Clock input
Supply voltage Ground Supply voltage for DQ
NC
Ground for DQ No connection
Document No. E0386E11 (Ver. 1.1) Date Published May 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003
EDS1232AATA
Ordering Information
Part number EDS1232AATA-60 EDS1232AATA-75 EDS1232AATA-60L EDS1232AATA-75L Supply voltage 3.3V Organization (words × bits) Internal Banks 4M × 32 4 Clock frequency MHz (max.) 166 133 133 100 166 133 133 100 /CAS latency 3 2 3 2 3 2 3 2 Package 86-pin plastic TSOP (II)
Part Number
E D S 12 32 A A TA - 60 L
Elpida Memory Type
D: Monolithic Device
Product Code S: SDRAM Density / Bank 12: 128M / 4-bank Bit Organization 32: x32 Voltage, Interface A: 3.3V, LVTTL Die Rev.
Spec. Detail Blank: Normal L: Low Power Speed 60: 166MHz/CL3 133MHz/CL2 75: 133MHz/CL3 100MHz/CL2 Package TA: TSOP (II)
Data Sheet E0386E11 (Ver. 1.1)
2
EDS1232AATA
CONTENTS Description...........1 Features......1 Pin Configurations ........ 1 Ordering Information.....2 Part Number ........ 2 Electrical Specifications......4 Block Diagram ..... 9 Pin Function.......10 Command Operation .. 11 Truth Table ........ 15 Simplified State Diagram ........... 21 Programming Mode Registers............22 Mode Register ............ 23 Power-up sequence....26 Operation of the SDRAM...........27 Timing Waveforms......43 Package Drawing ....... 50 Recommended Soldering Conditions .......... 51
Data Sheet E0386E11 (Ver. 1.1)
3
EDS1232AATA
Electrical Specifications
· All voltages are referenced to VSS (GND). · After power up, execute power up sequence and initialization sequence before proper device operation is achieved (refer to the Power up sequence). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating 0.5 to +4.6 0.5 to +4.6 50 1.0 0 to +70 55 to +125 Unit V V mA W °C °C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70°C) °
Parameter Supply voltage Input high voltage Input low voltage Symbol VDD, VDDQ VSS VIH VIL min. 3.0 0 2.0 0.3*2 typ. 3.3 0 max. 3.6 0 VDD + 0.3* 0.8
1
Unit V V V V
Notes
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width 5ns). 2. VIL (min.) = 1.5V (pulse width 5ns).
Data Sheet E0386E11 (Ver. 1.1)
4
EDS1232AATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V±0.3V, VSS, VSSQ = 0V) ° ±
Parameter /CAS latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current Refresh current Self refresh current Self refresh current (L-version) Symbol IDD1 IDD1 IDD2P IDD2PS Grade -60 -75 -60 -75 max. 120 105 120 105 1 1 Unit mA mA mA mA Test condition Burst length = 1 tRC tRC (min.) IO = 0mA One bank active CKE VIL (max.) tCK = 15ns CKE VIL (max.) tCK = CKE VIH (min.) tCK = 15ns CS VIH (min.) Input signals are changed one time during 30ns CKE VIH (min.) tCK = CKE VIL (max.) tCK = 15ns CKE VIL (max.), tCK = CKE VIH (min.), tCK = 15 ns, /CS VIH (min.), Input signals are changed one time during 30ns. CKE VIH (min.), tCK = , tCK tCK (min.), IO = 0mA, All banks active tRC tRC (min.) VIH VDD - 0.2V, VIL GND + 0.2V 2 3 Notes 1
IDD2N
20
mA
IDD2NS IDD3P IDD3PS
8 5 4
mA mA mA
IDD3N
25
mA
IDD3NS IDD4 IDD5 IDD6 IDD6 -xxL -60 -75 -60 -75
15 200 180 240 210 2.0 0.6
mA mA mA mA mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V±0.3V, VSS, VSSQ = 0V) ° ±
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. 1.0 1.5 2.4 -- max. 1.0 1.5 -- 0.4 Unit µA µA V V Test condition 0 = VIN = VDDQ, VDDQ = VDD, All other pins not under test = 0V 0 = VIN = VDDQ DOUT is disabled IOH = 2 mA IOL = 2 mA Notes
Data Sheet E0386E11 (Ver. 1.1)
5
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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