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Details, datasheet, quote on part number:A3024DL20A
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Datasheet text preview:
R
EM MICROELECTRONIC-MARIN SA
A3024
Very Low Power 8-Bit 32 kHz RTC with Digital Trimming, User RAM and High Level Integration
Features
n Digital trimming and temperature compensation facilities n Can be synchronized to 50 Hz or nearest s/min n 50 ns access time with 50 pF load capacitance n Standby on power down typically 1.2 mA n Universal interface compatible with both Intel and Motorola n Simple 8 bit interface with no delays or busy flags n 16 bytes of user RAM n Power fail input disables during power up / down or reset n Bus can be tri-state in power fail mode n Wide voltage range, 2.0 V to 5.5 V n 12 or 24 hour data formats n Time to 1/100 of a second n Leap year correction and week number calculation n Alarm and timer interrupts n Programmable interrupts: 10 ms, 100 ms, s or min n Sleep mode capability n Alarm programmable up to one month n Timer measures elapsed time up to 24 hours n Temperature range -40 to +85 OC n Packages DIP20 and SO20
Typical Operating Configuration
WR or R/W RD or DS IRQ
CPU
Address Decoder
Address Bus
Data Bus
CS IRQ RD X in WR A3024 A/D X out AD0 to AD7
Description
The A3024 is a low power CMOS real time clock. Standby current is typically 1.2 mA and the access time is 50 ns. The interface is 8 bits with multiplexed address and data bus. Multiplexing of address and data is handled by the input line A/D. There are no busy flags in the A3024, internal time update cycles are invisible to the user's software. Time data can be read from the A3024 in 12 or 24 hour data formats. An external signal puts the A3024 in standby mode. Even in standby, the A3024 pulls the IRQ pin active low on an internal alarm interrupt. Calendar functions include leap year correction and week number calculation. Time precision can be achieved by digital triming. The A3024 can be synchronized to an external 50 Hz signal or to the nearest second or minute. CS RD WR
RAM
Fig. 1
Pin Assignment
DIP20 / SO20
Applications
n n n n n Industrial controllers Alarm systems with periodic wake up PABX and telephone systems Point of sale terminals Automotive electronics
SYNC PF AD0 AD1 AD2 AD3 A/D IRQ VSS XIN
A3024
NC AD7 AD6 AD5 AD4 RD WR CS VDD XOUT Fig. 2
1
R
A3024
Absolute Maximum Ratings
Parameter
Maximum voltage at VDD Max. voltage at remaining pins Min. voltage on all pins Maximum storage temperature Minimum storage temperature Maximum electrostatic discharge to MIL-STD-883C method 3015 Maximum soldering conditions
Symbol Conditions
VDDmax Vmax Vmin TSTOmax TSTOmin VSmax TSmax VSS + 7.0V VDD + 0.3V VSS - 0.3V +125OC -55OC 1000V 250OC x 10s
or electric fields; however, it is advised that normal precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Operating temperature Logic supply voltage Supply voltage dv/dt (power-up & down) Decoupling capacitor Crystal Characteristics Frequency Load Capacitance Series resistance Symbol Min. Typ. Max. Units TA VDD dv/dt 100 f CL RS 32.768 8.2 12.5 35 50 -40 2.0 +85 5.0 5.5 6
O
C V
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
V/ms nF kHz pF kW Table 2
Handling Procedures
This device has built-in protection against high static voltages
7
Electrical Characteristics
VDD = 5.0V ± 10%, VSS = 0 V, TA = -40 to +85OC, unless otherwise specified
Parameter
Standby current
1)
Symbol Test Conditions
IDD IDD VDD = 3 V, PF = 0 VDD = 5 V, PF = 0 CS = 4 MHz, RD = VSS, WR = VDD IOL = 8 mA IOH = 1 mA, VDD = 2 V TA = +250C TA = +250C IOL = 6 mA IOH = 6 mA TA = +25 C VILS = 0.8 V VSS0
Min.
Typ.
1.2 2
Max.
10 15 1.5
Units
mA mA mA
Dynamic current
2)
IRQ (open drain) Output low voltage Output low voltage Inputs and Outputs Input logic low Input logic high Output logic low Output logic high PF activation voltage PF hysteresis Pullup on SYNC Input leakage Output tri-state leakage Oscillator Characteristics Starting voltage Start-up time Frequency Characteristics Frequency tolerance Frequency stability Temperature stability
1)
VOL VOL
0.4 0.4
V V
VIL VIH VOL VOH VPFL VH ILS IIN ITS VSTA VSTA TSTA Df/f fsta tsta
0.8 × VDD 2.4 0.5 × VDD 100 20 10 10 2 2.5 1
0.2 × VDD 0.4
1000 1000
V V V V V mV mA nA nA V V s
TA = +25 C addr. 10 hex = 00 hex 3) 2.0 £ VDD £ 5.5 V addr. 10 hex = 00 hex
O
210 1 see Fig. 5
4)
251 5
ppm ppm/V ppm Table 3
2) 3) 4)
With PFO = 0 (VSS) all I/O pads can be tri-state, tested. With PFO = 1 (VDD), CS = 1 (VDD) and all other I/O pads fixed to VDD or to VSS: same standby current, not tested. All other inputs to VDD and all outputs open. At a given temperature. See Fig. 4
2
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A3024
Typical Standby Current at VDD = 5 V
IDD [mA] 5 4 3 2 1 0 -50 25 50 80 95 TA [ C] Fig. 3
0
Typical standby current range at VDD = 5 V
Typical Frequency on IRQ
DF ppm F0 250 200 150 100 50 0 -50 -30 -10 10 30 50 70 90
Address 10 hex = 00 hex Quartz recommended 32.768 Hz ± 30 ppm with 8.2 pF load capacitance
TA [0C]
Fig. 4
Characteristic of a Quartz
DF F0 [ppm] -100 DF ppm 2 = - 0.038 O 2 (T - TO) ±10% FO C DF/FO = the ratio of the change in frequency to the nominal value expressed in ppm (It can be thought of as the frequency deviation at any temperature.) O = the temperature of interest in C T O TO = the turnover temperature (25 ±5 C) To determine the clock error (accuracy) at a given temperature, add O the frequency tolerance at 25 C to the value obtained from the formula above. TO-100 TO - 50 TO
O
Frequency ratio [ppm]
ma
x.
-200
-300
-400 TO+50 Temperature [ C] TO+100 T [OC]
min
.
Fig. 5
3
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A3024
Timing Characteristics
VDD = 5.0 ± 10%, VSS = 0 V, and TA = -40 to +85 C
Parameter Chip select duration, write cycle Write pulse duration Time between two transfers 1) RAM access time 2) Data valid to Hi-impedance 3) Write data settle time 4) Data hold time Advance write time PF response delay Rise time (all timing waveform signals) Fall time (all timing waveform signals) 5) CS delay after A/D CS delay to A/D
1)
0
Symbol tCS tWR tW tACC tDF tDW tDH tADW tPF tR tF tA/Ds tA/Dt
Test Conditions
Min. 50 50 100
Typ.
Max.
Units ns ns ns ns ns ns ns ns ns ns ns ns ns Table 4
CLOAD = 50 pF 10 50 10 10
50 30
60 40
100 200 200 5 10
tACC starts from RD (DS) or CS, whichever activates last Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF tDF starts from RD (DS) or CS, whichever deactivates first tDW ends at WR (R/W) or CS, whichever deactivates first tDH starts from WR (R/W) or CS, whichever deactivates first A/D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
2) 3) 4) 5)
Timing Waveforms
Read Timing for Intel (RD and WR pulse) and Motorola (DS or RD pin tied to CS, and R/W)
tF CS tA/Ds A/D
tCS tR
tW
tA/Dt RD/DS tACC tDF DATA DATA VALID Fig. 6a
4
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A3024
Intel Interface
Write Timing
tCS CS tA/Ds A/D RD tWR WR tDW DATA tDH Fig. 6b tA/Dt tW
DATA VALID
Write
CS RD WR A/D Valid Address Valid Data Fig. 6c
Data Bus D0 to D7
Read
CS RD WR A/D Valid Address Valid Data Fig. 6d
Data Bus D0 to D7
5
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