|
Details, datasheet, quote on part number:V4082
| |
Datasheet text preview:
EM MICROELECTRONIC - MARIN SA
V4082
Identification ROM
Description
The V4082 is a 64-bit read only memory (ROM) which contains a unique laser engraved serial number. The data in the ROM is partitioned into three sections: An 8bit identifier code, a 48-bit serial number and an 8-bit cyclical redundancy check (CRC). The serial number is incremented in fabrication such that no two parts have the same code. Communication for reading and writing is done serially via a single data lead (and ground return) using a 1-wire protocol. Power for reading is derived from the data line itself with no need for an extra power source. The circuit is available in SOT 223 or TO 92 package.
Features
Unique 48-bit silicon serial number gives 10 combinations Factory lasered and tested, no two parts alike 8-bit cyclic redundancy check ensures error-free reading Presence detect indicates to the system when first contact is made Zero standby power required Custom serial numbers available Pin compatible with DS 2400, DS 2401 in TO-92 and SOT-223
14
Applications
Socket identification PCB identification Equipment registration
Typical Operating Configuration
Vcc
Pin Assignment
TO -92
Vie w Fla t Front
on chip supply
SO T- 2 2 3
V SS 4 V 4082 1 2 3 V SS (G ND) DA TA
RPUP
5k
V 4082 1 23
DATA TX Control Logic + ROM 100 ohm MOSFET
1M RX Cext VSS
V SS (G ND)
SYSTEM
V4082
Fig. 1
Pin Name SOT-223 2 VSS 1 DATA 3 NC 4* VSS * Internally connected to pin 2
Pin TO92 1 2 3
DA TA N.C .
Function Ground return Serial data pin Ground return
Fig. 2
Copyright 2002, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
N.C .
V4082
Absolute Maximum Ratings
Parameter Voltage on Data Pin vs VSS Max. injected current into DATA pin Storage Temperature Power Dissipation Symbol VDATA Idata TSTD Pw Conditions -0.5 to 7.0V -20 to +20 mA -55 to +125 °C 10 mW
Table 1
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level.
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Operating Conditions
Parameter Symbol Min Typ External pull up voltage VCC 4.5 5 .0 External pull up resistance RPUP 5 External capacitance Cext Operating temperature TA -40 2 5 Max Unit 5.5 V k 800 pF + 85 °C
Table 2
Electrical Characteristics
Unless otherwise specified: All voltages are referenced to VSS, VDD= 5.0V, TA=-40 to +85°C. Parameter DC Characteristics Data Input Logic Low Data Input Logic High Sink Current Output Logic Low Output Logic High Input Resistance Operating Charge (after supply diode) Current consumption VIL VIH IL VOL VOH RIN COP Idata Modulator FET off Modulator FET on, 72 time slots Modulator FET off 1.2 30 16 VOUT = 0.4V I = 4mA -0.2 2.2 4.0 0.4 VCC* 0.4 VCC V V mA V V M nC µA
Table 3
Symbol
Test Conditions
Min
Typ
Max
Unit
* Depends on resistive divider RIN / (RPUP+RIN)
Timing Characteristics
Unless otherwise specified: VDD= 5.0V ±10%, TA=-40 to +85°C Parameter Time Slot Period Write 1 Low Time Write 0 Low Time Read Data Valid Read Data Setup Frame Sync Reset Low Time Reset High Time Presence Detect High Presence Detect Low Symbol TSLOT TLOW 1 TLOW 0 TRDV TSU TSYC TRSTL TRSTH TPDH TPDL 1 1 480 480 5 60 50 240 cf. remarks under "Effect of Cext" Min 60 1 60 Typ Max 120 15 120 15 Unit µs µs µs µs µs µs µs µs µs µs
Table 4
Test Conditions
Copyright 2002, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
V4082
Timing Waveforms
RESET PULSE/ PRESEN C E DETEC T
t SYC FIRST BIT OF 1-WIRE PROTOCOL
RESET PULSE DRIVEN LOW BY HOST
IDLE STATE
PRESENCE DETECT DRIVEN BY 1-WIRE DEVICE
t RSTL
t PDH
t PD L
t RSTH
Fig. 3
1-WIRE WRITE TIMING
tSYC tSLOT
W RITE 1
tLOW 1
Fig. 4a
tSYC tSLOT
W RITE 0 tLOW 0
Fig. 4b
Copyright 2002, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
|
|
