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Details, datasheet, quote on part number:V6108TBB
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Datasheet text preview:
R
EM MICROELECTRONIC-MARIN SA
V6108
40 Segment Static LCD Driver
Features
n Serial data input / output n Low dynamic current, 5 mA max. n Low standby current, 1 mA max. n Separate input and display voltages n Wide power supply range: VDD (logic) 2 to 8 V, VLCD (display) VDD to 12 V n On-chip latches separate control and display sections n Drives up to 40 LCD segments in direct drive n Crossfree cascadable n Schmitt Trigger on the inputs n 30 ns (typ.) glitch filter on every input n High noise immunity n Segment outputs short circuit protected n LCD blanking function O n - 40 to +85 C temperature range n On request extended temperature range, O - 40 to +125 C n QFP52 and TAB packages
Typical Operating Configuration
BP
SEG 2- 40
SEG 41- 80
V6108
D1 VLCD FR CLK STR R VGG VSS DQ
V6108
D1 VLCD FR CLK STR R VGG VSS DQ
Description
The V 6108 is a CMOS integrated circuit that drives LCD. The circuit drives up to 40 LCD segments from a serial clocked input. It has a serial output for cascading to further drives. The serially clocked data is parallel loaded into 40 latches under control of the strobe pin. The latched data determines which segments are ON or OFF. Any segment output can be used to drive a backplane. A blank function is provided to clear the display.
DI V LCD FR CLK STR R V DD VSS
Fig1
Pin Assignment
QFP52
n Balances and scales n Automotive displays n Utility meters n Large displays n Pagers n Portable, battery operated products n Telephones
S1 NC NC NC R STR DO VLCD VDD VSS DI CLK FR
S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14
52 40 39
Applications
1
V6108
13 14
26
27
S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28
Fig. 2
1
R
V6108
Absolute Maximum Ratings
Parameter
Logic supply voltage 1) LCD supply voltage Voltage at DI, CLK,STR, FR, R, DO Voltage at S1 to S40 Storage temperature range Power dissipation Electrostatic discharge max. to MIL-STD-883 C method 3015 Max. soldering conditions
1)
Handling Procedures
Conditions
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Symbol
-0.3V to +10V VDD -0.3V to +14V VLCD VLOGIC -0.3V to VDD+0.3V VDISP TSTO PMAX VSmax TS
VDD to VLCD + 0.3V
- 65 to +150 C 100 mW 1000V o 250 C x 10 s
o
Operating Conditions
Parameter
Operating temperature Logic supply voltage LCD supply voltage
1) 1)
Symbol Min. Typ. Max. Units
TA VDD VLCD -40 2.0 VDD +125 8 12
O
C V V
VLCD has to be higher or equal to VDD Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
The maximum operating temperature is confirmed Table 2 by sampling at initial device qualification. In o production, all devices are tested at +85 C. On o request devices tested at +125 C can be supplied.
Electrical Characteristics
VDD = 5V + 10%, VLCD = 12 V and TA = -40 to 85 C, unless otherwise specified
o
Parameter
Static supply current Static supply current Dynamic supply current Dynamic supply current All Input Signals Low level input voltage High level input voltage Leakage Input current Data Output DO High level output voltage Low level output voltage Driver Outputs S1...S40 High level output voltage Low level output voltage Short Circuit Current
1) 2)
Symbol Test Conditions
IDD ILCD IDD ILCD VIL VIH IIL VOH VOL VSH VSL ISC See note 1) See note 1)2) See note 1)3) See note
1)
Min.
Typ.
0.1 0.1
Max.
1 1
Units
µA µA µA µA V V µA mV mV mV mV mA Table 3
55
0.6
75
5 0.8
3.8 VIN =VSS or VIN =VDD IH = 100 µA VDD = VLCD = 4.5 V IL = 100 µA VDD = VLCD = 4.5 V IH = 20 µA, VDD = VLCD = 4.5 V IL = 20 µA, VDD = VLCD = 4.5 V VDD - 100
3.5 1
VSS + 100 VLCD- 100
only one output
0.9
VSS + 100
2
Tested with VIL= VSS, VIH= VDD Tested with fCL = 100 kHz, FDI= 50 kHz, 50 pF on each segment 3) Tested with fFL = 64 Hz, fCL= 0 Hz, 50 pF on each segment
Timing Characteristics
VDD = 5V ± 10%, VLCD = 12 V and TA = -40 to +85oC, unless otherwise specified Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation CLK falling to STR rising STR falling to CLK falling STR pulse width FR frequency Delay S1 - S40 fall time Delay S1 - S40 rise time 1) Recommended frame frequency.
Symbol Test Conditions
tCH tCL tCR tCF tDS tDH tPD tP tD tSTR fFR tSF tSR
2)
Min.
500 500
Typ.
Max.
500 500
Units
ns ns ns ns ns ns ns ns ns ns MHz µs µs
250 0 CLOAD = 50 pF 50 250 200
600
800
64 Hz 0.5 2.9 Maximum test frequency.
1)
1 1 5
2)
Table 4
2
R
V6108
Timing Waveforms
tCH CL tCL tCF tCR
Dl tDS DO
tDH
tPD
LD tP FL tSTR tD
S1
S40 tSR tSF Fig. 3
VOL S1 ... S40 versus VLCD at -40 C, +25 C and +85 C
100 90 80 TA = +850C 70 60 IOL= 20 mA VDD= 2 V
o
o
o
VOL [mV]
TA = +25 C 50 40 30 20 10 0 TA = -40 C
0
0
3
3.5
4
4.5
5
5.5
6
6.5
7
VLCD [V]
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
Fig. 4
3
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