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Details, datasheet, quote on part number:V61162
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Datasheet text preview:
EM MICROELCTRONIC-MARIN SA
V6116
Digitally Programmable 2, 4 and 8 Mux LCD Driver
Features
Typical Operating Conditions
V6116 mux mode 2 with 2 rows and 38 columns V6116 mux mode 4 with 4 rows and 36 columns V6116 mux mode 8 with 8 rows and 32 columns Low dynamic current, 250 µA max. Low standby current, 1 µA max. at +25 °C Voltage bias and mux signal generation on chip 2 display RAMs addressable as 8 x 40 words Display refresh on chip, dual RAM for display storage: 2 x (2 x 38; 4 x 36; 8 x 32) Column driver only mode to have 40 column outputs. Dual RAM for display storage: 2 x (2; 4; 8 x 40) Crossfree cascadable for large LCD applications Separate logic and LCD supply voltage pins Wide power supply range, VDD: 2 to 6 V, VLCD: 2 to 9 V Blank function for LCD blanking by data, BLANK bit and STR signal (STR only if internal Bias) All segments ON by data and SET bit Bit mapped Serial interface No busy state LCD updating synchronized to the LCD refresh signal TAB and bumped die form delivery. Other form delivery on request -40 to + 85 °C temperature range
V6116
Fig. 1
Pad Assignment
Description
The V6116 is a universal low multiplex LCD driver. The 2, 4 and 8 way multiplex is digitally programmable by the command byte. The display refresh is handled on chip via 2 selectable 8 x 40 RAMs which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 8 x 40 bit RAM (a set bit corresponds to an activated LCD pixel). Due to the very low driver impedance, the V6116 is designed to be provided in large pixel size applications. Using the TAB tools, the V6116 can be easily cascaded and it can be provided in very large display applications by using the column only driver command COL. The very low current consumption, the extremely large voltage range and the extremely wide temperature range give the V6116 a real advantage for a wide range of applications.
QFP52
Versions
V6116 060 with internal bias resistor V6116 020 without internal bias resistor When using the version 020 (without internal bias resistor) in mux mode 4, V3 has to be connected to VSS.
See Fig.16 for TAB pinout
Fig. 2
1
V6116
Absolute Maximum Ratings
Parameter
Supply voltage range LCD supply voltage range Voltage at DI, DO, CLK, STR, FR, COL Voltage at V1 to V3, S1 to S40 Storage temperature range Electrostatic discharge max. to MIL-STD-883C method 3015 Maximum soldering conditions
Handling Procedures
Conditions
-0.3 V to 9 V -0.3 V to 9.5 V
Symbol
VDD VLCD VLOGIC VDISP TSTO VSmax TSmax
-0.3 V to VDD +0.3 V -0.3 V to VLCD +0.3 V -65 to +150 °C 1000 V 290 °C x 15 s
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter
Operating temperature Logic supply voltage LCD supply voltage
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Symbol Min. Typ. Max. Unit
TA VDD VLCD -40 2 2 5 5 +85 6 9 °C V V
Table 2
Electrical Characteristics
VDD = 5 V ± 10%, VLCD = 2 to 7 V and TA = -40 to +85 °C, unless otherwise specified
Parameter
Dynamic supply current Dynamic supply current Dynamic supply current Dynamic supply current Standby supply current Control Signals DI, CLK, STR, FR and COL Input leakage Input capacitance Low level input voltage High level input voltage for DI, STR, FR and COL High level input voltage for CLK Data Output DO High level output voltage Low level output voltage Driver Outputs S1 ... S40 Driver impedance 4) Driver impedance 4) Driver impedance 4) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) DC output component
1) 2)
Symbol Test Conditions
ILCD IDD IDD IDD ISS See note 1) See note 1) at TA = 25 °C See note 1) See note 2) See note 3) at TA = 25 °C
Min.
Typ.
150 0.1 3 200 0.1
Max.
250 1 12 250 1
Units
µA µA µA µA µA
IIN CIN VIL VIH VIH
0 < VIN < VDD at TA = 25 °C 0 2.0 3.0
1 8
1000 0.8 V DD V DD
nA pF V V V
VOH VOL
IH = 4 mA IL = 4 mA
2.4 0.4
V V kW kW kW kW kW kW mV
RO U T RO U T RO U T RBIAS RBIAS RBIAS ± VDC
IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V see Tables 4a and 4b, VLCD = 5 V
1.0 2.6 7 18 20 24 30
1.5 3.5 24 27 50
All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD Table 3 All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD 3) All outputs open, all inputs at VDD 4) This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40) 5) This is the impedance seen at the segment pin. Outputs measured one at a time
2
V6116
Column Drivers
Outputs
S1 to S40 S1 to S40 S1 to S40 S1 to S40
FR Polarity
logic 1 logic 0 logic 1 logic 0
COL
logic 0 logic 0 logic 0 logic 0
Column Data
logic 1 logic 1 logic 0 logic 0
Measured
| Sx* - VSS | | VLCD - Sx* |
Guaranteed
| VLCD - Sx* | = | Sx* - VSS | ± 25 mV | VLCD - Sx* | | Sx* - VSS | | VLCD - Sx* | = | Sx* - VSS | ± 25 mV *Sx = the output number (I.e. S1 to S40)
Table 4a
Row Drivers
Outputs
S1 to Sn* S1 to Sn* S1 to Sn* S1 to Sn*
FR Polarity
logic 1 logic 0 logic 1 logic 0
COL
logic 1 logic 1 logic 1 logic 1
Row Data
logic 1 logic 1 logic 0 logic 0
Measured
| VLCD - Sx | | Sx - Vss |
Guaranteed
| VLCD - Sx | = | Sx - VSS | ± 25 mV | Sx - VSS | | VLCD - Sx | | VLCD - Sx | = | Sx - VSS | ± 25 mV *n= the V6116 mux programme number (i.e. 2, 4 or 8)
Table 4b
Timing Characteristics
VDD = 5 V ± 10%, VLCD = 2 to 7 V, and TA = -40 °C to +85 °C
Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling FR frequency (2/4/8)
1) 2)
Symbol Test Conditions
tC H tCL tCR tCF tDS tDH tPD tSTR tP tD fFR2)
Min.
120 120
Typ.
Max.
Units
ns ns ns ns ns ns ns ns ns ns Hz
200 200 201) 301) CLOAD = 50 pF 100 10 200 TA = 25 °C 128/256/512 100
tDS + tDH minimum must be ³ 100 ns. If tDS = 20 ns then tDH ³ 80 ns. V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number.
Table 5a
VDD = 2 to 6V, VLCD = 2 to 8 V, and TA = -40 °C to +85 °C
Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling FR frequency (2/4/8)
1) 2)
Symbol Test Conditions
tC H tCL tCR tCF tDS tDH tPD tSTR tP tD FFR2)
Min.
500 500
Typ.
Max.
Units
ns ns ns ns ns ns ns ns ns µs Hz
200 200 1001) 1501) CLOAD = 50 pF 500 10 1 128/256/512 400
tDS + tDH minimum must be ³ 500 ns. If tDS = 100 ns then tDH ³ 400 ns. V6116 n, FR = n times the desired LCD refresh rate where n is the V6116 mux mode number.
Table 5b
3
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