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Details, datasheet, quote on part number:V6118-2
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Datasheet text preview:
R
EM MICROELECTRONIC-MARIN SA
V6118
2, 4 and 8 Multiplex LCD Driver
Features
n n n n n n n n n n n n
Typical Operating Configuration
V6118 2 is 2 way multiplex with 2 rows and 38 columns V6118 4 is 4 way multiplex with 4 rows and 36 columns V6118 8 is 8 way multiplex with 8 rows and 32 columns Low dynamic current, 150 mA max. o Low standby current, 1 mA max. at 25 C Voltage bias and mux signal generation on chip Display refresh on chip, 40 x 8 RAM for display storage Display RAM addressable as 8, 40 bit words Column driver only mode to have 40 column outputs Crossfree cascadable for large LCD applications Separate logic and LCD supply voltage pins Wide power supply range, VDD: 2 to 6 V, VLCD: 2 to 8 V n BLANK function for LCD blanking on power up etc. n Voltage bias inputs for applications with large pixel sizes n Bit mapped n Serial input / output n Very low external component count o o n -40 C to +85 C temperature range n No busy states n LCD updating synchronized to the LCD refresh signal n QFP52 and TAB packages
8 row outputs
32 column outputs
V6118 8
VLCD FR DI DO CLK STR VDD COL VSS
Description
The V6118 is a universal low multiplex LCD driver. The version V6118 2 drives two ways multiplex (two blackplanes) LCD, the version V6118 4, four way multiplex LCD, and the V6118 8, eight way multiplex LCD. The display refresh is handled on chip via a 40 x 8 bit RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 40 x 8 bit RAM ( a set bit corresponds to an activated LCD pixel). The V6118 has very low dynamic current consumption, 150 mA max., making it particularly attractive for portable and battery powered applications. The wide operating range on both the logic (VDD) and the LCD (VLCD) supply voltages offers much application flexibility. The LCD bias generation is internal. The voltage bias levels can also be provided externally for applications having large pixels sizes. The V6118 can be used as a column only driver for cascading in large display applications. In the column only mode, 40 column outputs are available to address the display. A BLANK function is provided to blank the LCD, useful at power up to hold the display blank until the microprocessor has updated the display RAM.
VLCD FR DI CLK STR VDD VSS Fig. 1
Pin Assignment
QFP52
S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14
S1 V3 V2 V1 VLCD FR DI DO CLK STR VDD COL VSS
52
1
40 39
V6118
Applications
n Balances and scales n Automotive displays n Utility meters n Large displays (public information panels etc.) n Pagers n Portable, battery operated products n Telephones
13 14
27 26
S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27
See Fig.15 for the TAB pinout
S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28
Fig. 2
1
R
V6118
Absolute Maximum Ratings
Parameter
Supply voltage range LCD supply voltage range Voltage at DI, DO, CLK STR, FR, COL Voltage at V1 to V3, S1 to S40 Storage temperature range Power dissipation Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions
Handling Procedures
Conditions
-0.3 V to +8 V -0.3 V to +9 V -0.3 V to VDD+0.3V
Symbol
VDD VLCD VLOGIC VDISP TSTO PMAX VSMAX TS
-0.3 to VLCD+0.3V o - 65 to +150 C 100 mW
1000 V 250 oC x 10 s
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter
Operating temperature Logic supply voltage LCD supply voltage
Symbol Min. Typ. Max. Units
TA VDD VLCD -40 2 2 5 5 +85 6 8
O
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
C V V
Table 2
Electrical Characteristics
VDD = 5.0 V + 10%, VLCD = 2 to 7 V and TA = -40 to +85 C, unless otherwise specified Parameter
Dynamic supply current Dynamic supply current Dynamic supply current Dynamic supply current Standby supply current Control Signals DI, CLK, STR, FR and COL Input leakage Input capacitance Low level input voltage High level input voltage for DI, STR, FR and COL High level input voltage for CLK Data Output DO High level output voltage Low level output voltage Driver Outputs S1...S40 4) Driver impedance 4) Driver impedance 4) Driver impedance 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 DC output component
o
Symbol
ILCD IDD IDD IDD ISS
Test Conditions
See note 1) o See note at TA = + 25 C 1) See note 2) See note 3) o See note at TA = + 25 C
1)
Min.
Typ.
100 0.1 3 200 0.1
Max.
150 1 12 250 1
Units
µA µA µA µA µA
IIN CIN VIL VIH VIH VOH VOL ROUT ROUT ROUT RBIAS RBIAS RBIAS ±VDC
0 < VIN < VDD o at TA = + 25 C 0 2.0 3.0 IH = 4 mA IL = 4 mA IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V See tables 4a and 4b, VLCD = 5 V 2.4
1 8
100 0.8 VDD VDD
nA pF V V V V V kW kW kW kW kW kW mV Table 3
0.4 0.5 1.2 9 16 18 30 30 1.5 2.5 20 25
50
1) 2) 3) 4)
All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD. All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD. All outputs open, all inputs at VDD.
This is the impedance between the voltage bias level pins (V1, V2, or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40). 5) This is the impedance seen at the segment pin. Outputs measured one at a time.
2
R
V6118
Column Drivers
Outputs S1 to S40 S1 to S40
S1 to S40 S1 to S40
FR polarity logic 1 logic 0
logic 1 logic 0
COL logic 0 logic 0
logic 0 logic 0
Column data logic 1 logic 1
logic 0 logic 0
Measured | Sx* - VSS | | VLCD - Sx* |
| VLCD - Sx* | | Sx* - VSS |
Guaranteed
| VLCD - Sx* | = | Sx* - VSS | ± 25mV
| VLCD - Sx* | = | Sx* - VSS | ± 25 mV * Sx = the output no. (i.e. S1 to S40) Table 4a
Row Drivers
Outputs S1 to Sn* S1 to Sn*
S1 to Sn* S1 to Sn*
FR polarity logic 1 logic 0
logic 1 logic 0
COL logic 1 logic 1
logic 1 logic 1
Row data logic 1 logic 1
logic 0 logic 0
Measured
| VLCD - Sx | | Sx - VSS |
Guaranteed
| VLCD - Sx | = | Sx - VSS | ± 25mV | Sx - VSS | | VLCD - Sx |
| VLCD - Sx | = | Sx - VSS | ± 25 mV
Table 4b
* n = the V6118 version no. (i.e. 2, 4 or 8)
Timing Characteristics
VDD = 5.0 V ± 10%, VLCD = 2 to 8 V, and TA = -40 to +85oC Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling
1)
Symbol Test Conditions
tCH tCL tCR tCF tDS tDH tPD tSTR tP tD
2)
Min.
120 120
Typ.
Max.
Units
ns ns ns ns ns ns ns ns ns ns Hz
200 200 20 1) 30 CLOAD = 50 pF 100 10 200 100
1)
FFR FR frequency (Vers. 2/4/8) tDS + tDH minimum must be ³ 100 ns. If tDS = 20 ns then tDH ³ 80 ns. 2) V6118n. FR = n times the desired LCD refresh rate where n is the V6118 version number.
128/256/512
Table 5a
VDD = 2 to 6 V, VLCD = 2 to 8 V, and TA = -40 to +85oC Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling FR frequency (Vers. 2/4/8)
1) 2)
Symbol Test Conditions
tCH tCL tCR tCF tDS tDH tPD tSTR tP tD FFR
2)
Min.
500 500
Typ.
Max.
Units
ns ns ns ns ns ns ns ns ns ms Hz
200 200 100 1) 150 CLOAD = 50 pF 500 10 1 400
1)
128/256/512
tDS + tDH minimum must be ³ 500 ns. If tDS = 100 ns then tDH ³ 400 ns. V6118n, FR = n times the desired LCD refresh rate where n is the V6118 version number.
Table 5b
3
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