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Details, datasheet, quote on part number:PBL386102QNS
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Datasheet text preview:
February 1999
PBL 386 10/2 Subscriber Line Interface Circuit
Description
The PBL 386 10/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in PBX, Terminal adapters and other telecommunications equipment. The PBL 386 10/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 10/2 emulates a transformer equivalent dc-feed, programmable between 2x25 and 2x900 , with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 10/2 is compatible with loop start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 10/2 package is 28-pin PLCC.
Key Features
· Selectable overhead voltage principle All adaptive: The overhead voltage follows 0.6 VPeak < signals < 5 VPeak. Semi adaptive: The overhead voltage follows 2.5 VPeak < signals < 5 VPeak. · Metering 1.6Vrms · High and low battery with automatic switching · Battery supply as low as -10V · Only +5V in addition to GND and battery (VEE optional) · 35 mW on-hook power dissipation in active state · Long loop battery feed tracks VBat for maximum line voltage · 44V open loop voltage @ -48 V battery feed · Constant loop voltage for line leakage <5 mA · On-hook transmission · Full longitudinal current capability during on-hook
Ring Relay Driver
RRLY
DT DR TIPX RINGX HP TS
· Programmable loop & ring-trip detector threshold · Ground key detector · Analog temperature guard · Integrated Ring Relay Driver
Ring Trip Comparator Input Decoder and Control
C1 C2 C3 VCC DET
Ground Key Detector
PLC AOV VBAT2 VBAT
Off-hook Detector
PLD AGND VTX
BGND
VF Signal Transmission
RSN VEE
Figure 1. Block diagram.
28-pin plastic PLCC 1
38 PB 6L 10 /2
VEE
Two-wire Interface
Line Feed Controller and Longitudinal Signal Suppression
PSG LP REF
PBL 386 10/2
Maximum Ratings
Parameter Symbol Min Max Unit
Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 Power supply, 0°C TAmb +70°C VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND, continuous VBat with respect to BGND, 10 ms VBat2 with respect to A/BGND Power dissipation Continuous power dissipation at TAmb +70 °C Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage Ring relay current Ring trip comparator Input voltage Input current Digital inputs, outputs (C1, C2, C3, DET) Input voltage Output voltage (DET not active) Output current (DET) TIPX and RINGX terminals, 0°C 10 s, Note 2 TIPX or RINGX, pulse 10 s, Note 2 TIP or RING, pulse 10 s, Note 3
TStg T Amb TJ VCC VEE VBat VBat VBat2 PD VG
-55 -40 -40 -0.4 VBat -75 -80 VBat
+150 +110 +140 6.5 0.4 0.4 0.4 0.4 1.5
°C °C °C V V V V V W V V
-5
VCC BGND +13 75 mA
VDT, VDR IDT, IDR VID VOD I OD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA
VBat -5 -0.4 -0.4
VCC 5 VCC VCC 30
V mA V V mA
-110 VBat VBat - 20 VBat - 40 VBat - 70
+110 2 5 10 15
mA V V V V
Recommended Operating Condition
Parameter Symbol Min Max Unit
Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND
T Amb VCC VEE VBat VBat2
0 4.75 VBat -58 VBat
+70 5.25 -4.75 -10 -10
°C V V V V
Notes
1. 2. 3. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse 1µs is increased to the greater of |-70V| and |VBat -40V|. RF1 and RF2 20 are also required. Pulse is supplied to TIP and RING outside RF1 and RF2.
2
PBL 386 10/2
Electrical Characteristics
0 °C TAmb +70 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, RLC=18.7k, (IL = 27 mA), ZL = 600 , RLD = 50 k, RF1, RF2 = 0 , RRef = 15k, CHP = 68nF, CLP=0.33 µF, RT = 120 k, RSG = 24 k, RRX = 120 k, AOV- and VBat2-pin not connected, unless otherwise specified. Current definition: current is positive if flowing into a pin.
Ref fig
Parameter
Conditions
Min
Typ
Max
Unit
Two-wire port Overload level, VTRO Off-Hook, ILDC 10 mA On-Hook, ILDC 5 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM 2 Active state 1% THD, Note 1 2.5 1.4 Z T /200 20 35 VPeak VPeak /wire mArms /wire dB dB
Note 2 0 < f < 100 Hz active state 12 IEEE standard 455-1985,ZTRX = 736 0.2 kHz < f < 1.0 kHz 53 1.0 kHz < f < 3.4 kHz 53 3 active state 0.2 kHz f 1.0 kHz 1.0 kHz < f < 3.4 kHz 3 active state 0.2 kHz f 1.0 kHz 1.0 kHz < f < 3.4 kHz 4 active state 0.2 kHz < f < 3.4 kHz 59 59 53 53
70 70
Longitudinal to metallic balance, BLME E BLME = 20 · Log Lo VTR Longitudinal to four-wire balance, BLFE ELo BLFE = 20 · Log VTX Metallic to longitudinal balance, BMLE VTR BMLE = 20 · Log VLo
70 70
dB dB
70 70
dB dB
40
58
dB
Figure 2. Overload level, VTRO, two-wire port
RL VTRO
C
TIPX
VTX
ILDC
1 << R , R = 600 L L C RT = 120 k, RRX = 120 k
PBL 386 10/2
RINGX RSN
RT
E RX
RRX
Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance
1 C << 150 , RLR = RLT = RL /2= 300
TIPX ELo C R LT V TR R LR RINGX
VTX
PBL 386 10/2
RSN
RT
V TX
R RX
RT = 120 k, RRX = 120 k
3
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